Hi Gilles, I did the changes, but the kernel is not booting. I got the message from serial: U-Boot 2013.01-00058-g5957f6d (Feb 11 2013 - 08:42:43) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: SABRE Lite DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected SST25VF016B with page size 4 KiB, total 2 MiB *** Warning - bad CRC, using default environment
auto-detected panel HDMI enable_hdmi: setup HDMI monitor Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: using phy at 6 FEC [PRIME] Warning: FEC using MAC address from net device Hit any key to stop autoboot: 0 AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part No port device detected! ** Bad device size - sata 0 ** ** Bad device size - sata 0 ** SATA device 1: unknown device ** Bad device sata 1 ** ** Bad device sata 1 ** MMC: no card present mmc0(part 0) is current device MMC: no card present ** Bad device mmc 0 ** MMC: no card present ** Bad device mmc 0 ** mmc1 is current device ** Unrecognized filesystem type ** 2627 bytes read in 30 ms (85 KiB/s) ## Executing script at 10008000 Setting bus to 2 Valid chip addresses: ------ no Freescale display Valid chip addresses: ------ no ft5x06 touch controller Valid chip addresses: ------ no 800x480 display ** File not found /boot/imx6q-sabrelite.dtb ** only CEA modes allowed on HDMI port 3997932 bytes read in 378 ms (10.1 MiB/s) ## Booting kernel from Legacy Image at 10800000 ... Image Name: Linux-3.0.35-ipipe Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3997868 Bytes = 3.8 MiB Load Address: 10008000 Entry Point: 10008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. Linux version 3.0.35-ipipe (bruno@bruno-Inspiron-N5010) (gcc version 4.8.2 20131014 (prerelease) (crosstool-NG linaro-1.13.1-4.8-2013.10 - Lina4 CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: Boundary Devices Nitrogen6X/SABRE Lite Board Memory policy: ECC disabled, Data cache writealloc CPU identified as i.MX6Q, silicon rev 1.2 PERCPU: Embedded 10 pages/cpu @8c008000 s16640 r8192 d16128 u40960 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 227328 Kernel command line: enable_wait_mode=off video=mxcfb0:dev=hdmi,1280x720M@60,if=RGB24,bpp=32 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off1 PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 640MB 256MB = 896MB total Memory: 899816k/899816k available, 148760k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xf4600000 - 0xffe00000 ( 184 MB) vmalloc : 0xc0800000 - 0xf2000000 ( 792 MB) lowmem : 0x80000000 - 0xc0000000 (1024 MB) pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) modules : 0x7f000000 - 0x7fe00000 ( 14 MB) .init : 0x80008000 - 0x80046000 ( 248 kB) .text : 0x80046000 - 0x8077fdec (7400 kB) .data : 0x80780000 - 0x807ddba0 ( 375 kB) .bss : 0x807ddbc4 - 0x8084f644 ( 455 kB) SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 Preemptible hierarchical RCU implementation. NR_IRQS:624 MXC GPIO hardware sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655ms arm_max_freq=1GHz MXC_Early serial console at MMIO 0x21e8000 (options '115200') bootconsole [ttymxc1] enabled I-pipe 1.18-13: pipeline enabled. Console: colour dummy device 80x30 Calibrating delay loop... 1581.05 BogoMIPS (lpj=7905280) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok I-pipe, 396.000 MHz timer I-pipe, 396.000 MHz clocksource hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available CPU1: Booted secondary processor CPU2: Booted secondary processor CPU3: Booted secondary processor Brought up 4 CPUs SMP: Total of 4 processors activated (6324.22 BogoMIPS). devtmpfs: initialized print_constraints: dummy: NET: Registered protocol family 16 print_constraints: vddpu: 725 <--> 1300 mV at 1150 mV fast normal print_constraints: vddcore: 725 <--> 1300 mV at 1150 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal print_constraints: vdd3p0: 2625 <--> 3400 mV at 3000 mV fast normal lcd_disable_pins ------------ Board type Sabre Lite imx_add_mxc_pwm:pdata= (null) imx_add_mxc_pwm:pdata= (null) imx_add_mxc_pwm:pdata=807a82d0 imx_add_mxc_pwm:pdata= (null) Flexcan NXP tja1040 hw-breakpoint: found 6 breakpoint and 1 watchpoint registers. hw-breakpoint: 1 breakpoint(s) reserved for watchpoint single-step. hw-breakpoint: maximum watchpoint size is 4 bytes. L310 cache controller enabled Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP Modules linked in: CPU: 1 Not tainted (3.0.35-ipipe #6) PC is at 0xbffac2f0 LR is at update_process_times+0x44/0x70 pc : [<bffac2f0>] lr : [<8008d230>] psr: 00000193 sp : bffadef8 ip : 00000001 fp : 00000000 r10: bffac010 r9 : 40063ff0 r8 : 00000001 r7 : 8c012040 r6 : 8004496c r5 : 8079aae0 r4 : 20000013 r3 : 80041838 r2 : bff8e1c0 r1 : 20000193 r0 : 00000001 Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7d Table: 1000404a DAC: 00000015 Process swapper (pid: 0, stack limit = 0xbffac2f0) Stack: (0xbffadef8 to 0xbffae000) dee0: 00000001 00000001 df00: 8079aae0 8004496c 00000000 00000001 8079aae0 8c01283c 00000000 800461e4 df20: 800411b8 00000020 807ea400 807ea3e0 00000001 800bef80 807ea404 80056940 df40: 807abea0 80041838 80044518 807ea3e0 00000000 bffadf80 f2a00100 0000001d df60: 805b2cec 8079e1ec bffac000 00000000 00000000 80056a8c ffffffff 8004bc00 df80: 20000000 0000001d 20000000 f40dc010 8c012838 bffac000 807ddc84 805b2cec dfa0: 8079e1ec 412fc09a 00000000 00000000 00000001 bffadfc8 8005cdb4 8005b56c dfc0: 20000013 ffffffff 805b2cec 00000001 412fc09a 8004cee0 bffac000 8004d04c dfe0: 4ffb006a 00000015 10c03c7d 807dde38 1000406a 105a4614 00000000 00000000 Unable to handle kernel paging request at virtual address 00303068 pgd = 80004000 [00303068] *pgd=00000000 Unable to handle kernel NULL pointer dereference at virtual address 00000000 Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = 80004000 pgd = 80004000 [00000000] *pgd=00000000 [00000000] *pgd=00000000 Unable to handle kernel paging request at virtual address f0000000 pgd = 80004000 [f0000000] *pgd=00000000 Thanks, Bruno Em Domingo, 23 de Fevereiro de 2014 20:37, Gilles Chanteperdrix <[email protected]> escreveu: On 02/24/2014 12:32 AM, Bruno Tunes de Mello wrote: > ^C---|-----------|-----------|-----------|--------|------|------------------------- > RTS| 3.636| 12.446| 1383.499| 5| 0| 00:00:39/00:00:39 > > Could you say if these results are right or not. They are not right. Could you try the following (kernel) patch? diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c index 3cf6b22..d1b74e9 100644 --- a/arch/arm/mach-mx6/mm.c +++ b/arch/arm/mach-mx6/mm.c @@ -97,7 +97,7 @@ void __init mx6_map_io(void) #ifdef CONFIG_CACHE_L2X0 int mxc_init_l2x0(void) { - unsigned int val; + unsigned int val, aux_ctrl; #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 @@ -114,12 +114,24 @@ int mxc_init_l2x0(void) val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); val |= 0x40800000; writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); +#ifndef CONFIG_IPIPE val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); val |= L2X0_DYNAMIC_CLK_GATING_EN; val |= L2X0_STNDBY_MODE_EN; writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); +#endif + + aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | + (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | + (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT) | + (1 << 23) | + (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | + (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | + (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | + (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); + + l2x0_init(IO_ADDRESS(L2_BASE_ADDR), aux_ctrl, L2X0_AUX_CTRL_MASK); - l2x0_init(IO_ADDRESS(L2_BASE_ADDR), 0x0, ~0x00000000); return 0; } diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 1e2c52d..27550b3 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -421,6 +421,9 @@ void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) writel_relaxed(1, l2x0_base + L2X0_CTRL); } + /* Re-read it in case some bits are reserved. */ + aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + outer_cache.inv_range = l2x0_inv_range; outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range; -- Gilles. _______________________________________________ Xenomai mailing list [email protected] http://www.xenomai.org/mailman/listinfo/xenomai
