thanks vary mach , I disable perf and have a try .Yes ,the auxiliary register
has bit 23 set (0x800000), and has L2 write
allocate disabled.
在 2014-03-29 01:35:33，"Gilles Chanteperdrix" <[email protected]>
写道：
>On 03/28/2014 06:02 AM, 嵌入式工程师 wrote:
>> This is my logs
>>
>>
>>
>>
> > (...)
>> hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
>
>I guess you should probably not enable perf. On some architectures, it
>creates unwanted latencies, by using NMI.
>
> > (...)
>> l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x02870000, Cache size: 1048576
>> B
>
>So, your auxiliary register has bit 23 set (0x800000), and has L2 write
>allocate disabled.
>
>--
> Gilles.
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