On Mon, Nov 17, 2014 at 11:15:42PM +0100, Gilles Chanteperdrix wrote: > On Mon, Nov 17, 2014 at 05:10:01PM -0500, Lennart Sorensen wrote: > > Not sure anything there looks that big. I wonder if the gpio bank is > > just slow to generate the IRQ in the first place for some reason.
And yes it was. > No, I do not see anything wrong either. One thing that could delay > gpio irq delivery is PIC muting, if it has a bug with this SOC, so I > strongly suggest (once again) that you comment out PIC muting as > long as you have issues. Anyway, I do not think that is the case > here. > > If the latency is not always off, you should trigger a trace only > when you detect that the latency is to large. OK, found the problem. The GPIO bank is by default (in the kernel, not hardware) configured for 'SmartIdle' which apparently means it goes to sleep and first has to wake up, power everything up, start the clock, then measure the state of the pin for a couple of clocks before generating an IRQ. Turning off idle support entirely on the GPIO bank makes it consistently about 30us response time, so that is great. -- Len Sorensen _______________________________________________ Xenomai mailing list [email protected] http://www.xenomai.org/mailman/listinfo/xenomai
