I'm quoting out of context as they were discussing the design of the
Inferno VM but Phil Winterbottom & Rob Pike mention in
http://www.vitanuova.com/inferno/papers/hotchips.html :
"One might argue that a stack-based processor design would mitigate the
difficulties, but our experience with the implementation of a stack
machine in the AT&T Crisp microprocessor [5] leads us to believe that
stack architectures are inherently slower than register-based machines.
Their design lengthens the critical path by replacing simple registers
with a complex stack cache mechanism."
5. Ditzel, D. R. and McLellan, R., ``Register Allocation for Free: The C
Machine Stack Cache'', Proc. of Symp. on Architectural Support for
Programming Languages and Operating Systems, March, 1982, pp. 48-56.
I found the paper at http://portal.acm.org/citation.cfm?id=960120.801825
but you have to have a paid account so I have no idea of their
conclusions beyond Rob & Phil's comment
It is a widely cited paper though, so it must be a good read. (and I did
find loads of other great stuff while trying to find it)
The Crisp sounds like something interesting, anyone know much about it?
I found this again at acm
Design tradeoffs to support the C programming language in the CRISP
microprocessor
http://portal.acm.org/citation.cfm?id=36198&coll=portal&dl=ACM
and this at ieee
CRISP: a pipelined 32-bit microprocessor with 13-kbit of cache memory
http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/4/22616/01052813.pdf
seems that information doesn't want to be free today
I've got some time to delve into Fascicle One again and indeed, MMIX
doesn't have any stack at all. When you need stack, you implement it
yourself. Anyone knows of other CPU's using this method for stack
(i.e. no in-built support for stack in memory)? There is stack based
on registers, though.
