https://bugzilla.kernel.org/show_bug.cgi?id=220705
--- Comment #43 from Lukas Wunner ([email protected]) --- The dmesg output shows that the L1 Substates are already disabled when the kernel enumerates the wifi card, so the kernel is not the culprit. Looking at the coreboot source code I noticed that the "PCIe L1 Substates" BIOS menu entry you've taken a picture of is only meaningful on Alderlake and Meteorlake platforms. It's disregarded on Skylake (which is what the Pixelbook Eve uses). However coreboot aggressively enables all L1 Substates when it scans the PCI bus. I took another look at the lspci output you've provided and noticed a key difference: The Root Port at 00:1c.0 is missing the L1 PM Substates extended capablity at offset 0x200. Compare this to the lspci output provided by Adrià: https://bugzilla.kernel.org/attachment.cgi?id=308858 This entire portion is missing: - Capabilities: [200 v1] L1 PM Substates - L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ - PortCommonModeRestoreTime=40us PortTPowerOnTime=44us - L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- - T_CommonMode=40us LTR1.2_Threshold=106496ns - L1SubCtl2: T_PwrOn=60us That's the reason why coreboot can't enable the L1 Substates on the wifi card. It can only do so if the Root Port supports L1 Substates as well. The hardware revision is 0x1f in both cases, so it doesn't look like your PCH has a different stepping. I don't really know why it's not exposing the L1 PM Substates extended capability. Could you attach the output of "sudo lspci -vvvxxxx -s 00:1c.0"? This will include a hexdump of config space and will allow us to see what we've got at offset 0x200. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ acpi-bugzilla mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/acpi-bugzilla
