THz communication isn't where you'll find solutions for the same reason that CPU clock speeds have stalled: The radius of control of a CPU runs into speed of light limits.
I'm discussing with the Numenta guys <https://discourse.numenta.org/t/iram-chips-and-sparse-representation/8520> their (FPGA) approach to silicon connectivity yielding sparse representation vs mine <https://jimbowery.blogspot.com/2013/04/a-circuit-minimizing-multicore-shared.html> reflecting our respective biases that boil down to (mine) white matter interconnect and (their) gray matter interconnect (ie: cortical columns). If you look at the illustration my link you'll notice a line of CPUs along the bottom with the rest of the die area occupied by interleaved banks of crossbar switch memories all shared with the CPUs. They think the intensive computation done by cortical columns is the place to focus work and that local memories to a much larger number of processors works because the sparse (bit) vectors representing intra-column connections and activations are short enough that you don't even need to do run length encoding -- and you can leave the white matter interconnects as an after-thought involving far slower communications layers. I think that if you optimize for the hard problem of global communication first, you can degenerate much more gracefully to the kind of optimizations they see as central to the problem they're trying to solve (decoding the cortical column's function). Neither of us, however, is really thinking outside the box about "growing" and "pruning" physical interconnects. On Thu, Aug 12, 2021 at 10:50 AM <magnuswootto...@gmail.com> wrote: > I don't know about neuroscience, I'm not into it myself ethically. > > Performance-wise, the thing I'm currently into is Pipe-lining FPGA's, to > support higher clock rates by making the pathway the electricity takes from > input to output a shorter distance, hence a smaller electrical delay. > Simply you're just dropping off to a register after every so gates, and > then the next stage picks it up from where the last one dropped it off, it > runs like a factory assembly line. > > That could get you to a terrahert if it was a millimetre between each > stage, but the strange thing about it is I dont see much on the internet > except a few people wondering about it and never actually doing it for > real. So the reality of it I'm not sure of, maybe everyone is stuffing it > up? Have to get a cheap FPGA (~$100) and test it out myself. > *Artificial General Intelligence List <https://agi.topicbox.com/latest>* > / AGI / see discussions <https://agi.topicbox.com/groups/agi> + > participants <https://agi.topicbox.com/groups/agi/members> + > delivery options <https://agi.topicbox.com/groups/agi/subscription> > Permalink > <https://agi.topicbox.com/groups/agi/T1dc2a5f2d1d491d4-M93919bbb643dc3cf93a0202c> > ------------------------------------------ Artificial General Intelligence List: AGI Permalink: https://agi.topicbox.com/groups/agi/T1dc2a5f2d1d491d4-Mcd595361f505da028b3f6f8b Delivery options: https://agi.topicbox.com/groups/agi/subscription
