[Public]
Reviewed-by: Prike Liang <[email protected]>
Regards,
Prike
> -----Original Message-----
> From: amd-gfx <[email protected]> On Behalf Of Alex
> Deucher
> Sent: Saturday, October 11, 2025 5:15 AM
> To: [email protected]
> Cc: Deucher, Alexander <[email protected]>
> Subject: [PATCH 1/7] drm/amdgpu: drop unused structures in amdgpu_drm.h
>
> These were never used and are duplicated with the interface that is used.
> Maybe
> leftovers from a previous revision of the patch that added them.
>
> Fixes: 90c448fef312 ("drm/amdgpu: add new AMDGPU_INFO subquery for userq
> objects")
> Signed-off-by: Alex Deucher <[email protected]>
> ---
> include/uapi/drm/amdgpu_drm.h | 21 ---------------------
> 1 file changed, 21 deletions(-)
>
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index
> 3cb316ad54b34..e5252bf597b36 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -1564,27 +1564,6 @@ struct drm_amdgpu_info_hw_ip {
> __u32 userq_num_slots;
> };
>
> -/* GFX metadata BO sizes and alignment info (in bytes) */ -struct
> drm_amdgpu_info_uq_fw_areas_gfx {
> - /* shadow area size */
> - __u32 shadow_size;
> - /* shadow area base virtual mem alignment */
> - __u32 shadow_alignment;
> - /* context save area size */
> - __u32 csa_size;
> - /* context save area base virtual mem alignment */
> - __u32 csa_alignment;
> -};
> -
> -/* IP specific fw related information used in the
> - * subquery AMDGPU_INFO_UQ_FW_AREAS
> - */
> -struct drm_amdgpu_info_uq_fw_areas {
> - union {
> - struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
> - };
> -};
> -
> struct drm_amdgpu_info_num_handles {
> /** Max handles as supported by firmware for UVD */
> __u32 uvd_max_handles;
> --
> 2.51.0
