[Public]
Reviewed-by: Prike Liang <[email protected]>
Regards,
Prike
> -----Original Message-----
> From: amd-gfx <[email protected]> On Behalf Of Alex
> Deucher
> Sent: Saturday, October 11, 2025 5:15 AM
> To: [email protected]
> Cc: Deucher, Alexander <[email protected]>
> Subject: [PATCH 4/7] drm/amdgpu/sdma: add query for CSA size and alignment
>
> Needed to query the CSA size and alignment for SDMA user queues.
>
> Signed-off-by: Alex Deucher <[email protected]>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 7 +++++++
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 12 ++++++++++++
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 12 ++++++++++++
> 3 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index 34311f32be4c6..872d81f73244a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -50,6 +50,11 @@ enum amdgpu_sdma_irq {
>
> #define NUM_SDMA(x) hweight32(x)
>
> +struct amdgpu_sdma_csa_info {
> + u32 size;
> + u32 alignment;
> +};
> +
> struct amdgpu_sdma_funcs {
> int (*stop_kernel_queue)(struct amdgpu_ring *ring);
> int (*start_kernel_queue)(struct amdgpu_ring *ring); @@ -133,6 +138,8 @@
> struct amdgpu_sdma {
> struct list_head reset_callback_list;
> bool no_user_submission;
> bool disable_uq;
> + void (*get_csa_info)(struct amdgpu_device *adev,
> + struct amdgpu_sdma_csa_info *csa_info);
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index aa89d915d3f98..ae1e7eb677749 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1282,6 +1282,17 @@ static void sdma_v6_0_set_ras_funcs(struct
> amdgpu_device *adev)
> }
> }
>
> +/* all sizes are in bytes */
> +#define SDMA6_CSA_SIZE 32
> +#define SDMA6_CSA_ALIGNMENT 4
> +
> +static void sdma_v6_0_get_csa_info(struct amdgpu_device *adev,
> + struct amdgpu_sdma_csa_info *csa_info) {
> + csa_info->size = SDMA6_CSA_SIZE;
> + csa_info->alignment = SDMA6_CSA_ALIGNMENT; }
> +
> static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) {
> struct amdgpu_device *adev = ip_block->adev; @@ -1314,6 +1325,7 @@
> static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
> sdma_v6_0_set_irq_funcs(adev);
> sdma_v6_0_set_mqd_funcs(adev);
> sdma_v6_0_set_ras_funcs(adev);
> + adev->sdma.get_csa_info = &sdma_v6_0_get_csa_info;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 84d0e1aa4d501..3c32b5161739d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1267,6 +1267,17 @@ static void
> sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); }
>
> +/* all sizes are in bytes */
> +#define SDMA7_CSA_SIZE 32
> +#define SDMA7_CSA_ALIGNMENT 4
> +
> +static void sdma_v7_0_get_csa_info(struct amdgpu_device *adev,
> + struct amdgpu_sdma_csa_info *csa_info) {
> + csa_info->size = SDMA7_CSA_SIZE;
> + csa_info->alignment = SDMA7_CSA_ALIGNMENT; }
> +
> static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) {
> struct amdgpu_device *adev = ip_block->adev; @@ -1300,6 +1311,7 @@
> static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
> sdma_v7_0_set_vm_pte_funcs(adev);
> sdma_v7_0_set_irq_funcs(adev);
> sdma_v7_0_set_mqd_funcs(adev);
> + adev->sdma.get_csa_info = &sdma_v7_0_get_csa_info;
>
> return 0;
> }
> --
> 2.51.0
