On 10/28/25 23:06, Timur Kristóf wrote: > Based on research carried out by Alexandre and Christian. > > VCE1 actually executes its code from the VCPU BO. > Due to various hardware limitations, the VCE1 requires > the VCPU BO to be in the low 32 bit address range. > However, VRAM is typically mapped at the high address range, > which means the VCPU can't access VRAM through the FB aperture. > > To solve this, we write a few page table entries to > map the VCPU BO in the GART address range. And we make sure > that the GART is located at the low address range. > That way the VCE1 can access the VCPU BO. > > Signed-off-by: Timur Kristóf <[email protected]> > Co-developed-by: Alexandre Demers <[email protected]> > Signed-off-by: Alexandre Demers <[email protected]> > Co-developed-by: Christian König <[email protected]> > Signed-off-by: Christian König <[email protected]>
Make that a suggested-by and drop co-developed and signed-off-by for me. The code was solely written by you if I'm not completely mistaken. Patch itself is Reviewed-by: Christian König <[email protected]> Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 44 +++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > index e62fd8ed1992..27f70146293d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > @@ -34,6 +34,7 @@ > > #include "amdgpu.h" > #include "amdgpu_vce.h" > +#include "amdgpu_gart.h" > #include "sid.h" > #include "vce_v1_0.h" > #include "vce/vce_1_0_d.h" > @@ -46,6 +47,11 @@ > #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) > #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 > > +#define VCE_V1_0_GART_PAGE_START \ > + (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) > +#define VCE_V1_0_GART_ADDR_START \ > + (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) > + > static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); > static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); > > @@ -535,6 +541,38 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block > *ip_block) > return 0; > } > > +/** > + * vce_v1_0_ensure_vcpu_bo_32bit_addr() - ensure the VCPU BO has a 32-bit > address > + * > + * @adev: amdgpu_device pointer > + * > + * Due to various hardware limitations, the VCE1 requires > + * the VCPU BO to be in the low 32 bit address range. > + * Ensure that the VCPU BO has a 32-bit GPU address, > + * or return an error code when that isn't possible. > + */ > +static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) > +{ > + const u64 gpu_addr = amdgpu_bo_gpu_offset(adev->vce.vcpu_bo); > + const u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); > + const u64 max_vcpu_bo_addr = 0xffffffff - bo_size; > + > + /* Check if the VCPU BO already has a 32-bit address. > + * Eg. if MC is configured to put VRAM in the low address range. > + */ > + if (gpu_addr <= max_vcpu_bo_addr) > + return 0; > + > + /* Check if we can map the VCPU BO in GART to a 32-bit address. */ > + if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) > + return -EINVAL; > + > + amdgpu_gart_bind_vram_bo(adev, VCE_V1_0_GART_ADDR_START, > adev->vce.vcpu_bo, > + AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID); > + adev->vce.gpu_addr = adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; > + return 0; > +} > + > static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) > { > struct amdgpu_device *adev = ip_block->adev; > @@ -554,6 +592,9 @@ static int vce_v1_0_sw_init(struct amdgpu_ip_block > *ip_block) > if (r) > return r; > r = vce_v1_0_load_fw_signature(adev); > + if (r) > + return r; > + r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); > if (r) > return r; > > @@ -669,6 +710,9 @@ static int vce_v1_0_resume(struct amdgpu_ip_block > *ip_block) > if (r) > return r; > r = vce_v1_0_load_fw_signature(adev); > + if (r) > + return r; > + r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); > if (r) > return r; >
