On Wed, 2025-10-29 at 19:46 +0000, Deucher, Alexander wrote: > [Public] > > > -----Original Message----- > > From: Koenig, Christian <[email protected]> > > Sent: Wednesday, October 29, 2025 8:02 AM > > To: Timur Kristóf <[email protected]>; > > [email protected]; > > Deucher, Alexander <[email protected]>; Alexandre Demers > > <[email protected]>; Rodrigo Siqueira > > <[email protected]>; Liu, > > Leo <[email protected]> > > Subject: Re: [PATCH 14/14] drm/amdgpu/vce1: Tolerate VCE PLL > > timeout better > > > > On 10/28/25 23:06, Timur Kristóf wrote: > > > Sometimes the VCE PLL times out while we are programming it. > > > When it happens, the VCE still works, but much slower. > > > Observed on some Tahiti boards, but not all: > > > - FirePro W9000 has the issue > > > - Radeon R9 280X not affected > > > - Radeon HD 7990 not affected > > > > > > Continue the complete VCE PLL programming sequence even when it > > > timed > > > out. With this, the VCE will work fine and faster after the > > > timeout > > > happened. > > > > Mhm, interesting. No idea what could be causing this. > > > > Not sure if just ignoring the error is ok or not. @Alex? > > Looks like these registers can also be accessed indirectly via a > different index/data accessor besides SMC. I don't know whether it > matters or not.
I've tried various things to work around this issue, including the indirect accessors that Alex suggested, but they didn't help with the timeout. After some trial and error I think that on this one specific chip, the PLL takes forever to wake from sleep mode. Unfortunately, just increasing the delays or adding an extra timeout does not solve it. However, if I never put the PLL into sleep mode in si_set_vce_clocks then the timeout never happens. It works if I either just leave the PLL in bypass mode or if I put it in reset mode when turning the VCE clocks off. I would lean towards leaving it in bypass mode, because that seems to be the least risky and simplest solution. Does that sound OK to you guys? Thanks, Timur
