[Public] > -----Original Message----- > From: Koenig, Christian <[email protected]> > Sent: Wednesday, October 29, 2025 8:02 AM > To: Timur Kristóf <[email protected]>; [email protected]; > Deucher, Alexander <[email protected]>; Alexandre Demers > <[email protected]>; Rodrigo Siqueira <[email protected]>; Liu, > Leo <[email protected]> > Subject: Re: [PATCH 14/14] drm/amdgpu/vce1: Tolerate VCE PLL timeout better > > On 10/28/25 23:06, Timur Kristóf wrote: > > Sometimes the VCE PLL times out while we are programming it. > > When it happens, the VCE still works, but much slower. > > Observed on some Tahiti boards, but not all: > > - FirePro W9000 has the issue > > - Radeon R9 280X not affected > > - Radeon HD 7990 not affected > > > > Continue the complete VCE PLL programming sequence even when it timed > > out. With this, the VCE will work fine and faster after the timeout > > happened. > > Mhm, interesting. No idea what could be causing this. > > Not sure if just ignoring the error is ok or not. @Alex?
Looks like these registers can also be accessed indirectly via a different index/data accessor besides SMC. I don't know whether it matters or not. The other indirect accessors are: #define mmCG_IND_ADDR 0x023C #define mmCG_IND_DATA 0x023D And the indirect indexes are: #define ixCG_VCEPLL_FUNC_CNTL 0x0600 #define ixCG_VCEPLL_FUNC_CNTL_2 0x0601 #define ixCG_VCEPLL_FUNC_CNTL_3 0x0602 #define ixCG_VCEPLL_FUNC_CNTL_4 0x0603 #define ixCG_VCEPLL_FUNC_CNTL_5 0x0604 #define ixCG_VCEPLL_STATUS 0x0605 #define ixCG_VCEPLL_SPREAD_SPECTRUM 0x0606 #define ixCG_VCEPLL_SPREAD_SPECTRUM_2 0x0607 // CG_VCEPLL_FUNC_CNTL #define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET_MASK 0x00000001L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_SLEEP_MASK 0x00000002L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_BYPASS_EN_MASK 0x00000004L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLREQ_MASK 0x00000008L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_REFCLK_SEL_MASK 0x00000030L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKF_UPDATE_MASK 0x00000040L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKR_UPDATE_MASK 0x00000080L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET_EN_MASK 0x00000100L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_VCO_MODE_MASK 0x00000600L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_REF_DIV_MASK 0x003f0000L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK_MASK 0x40000000L #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK2_MASK 0x80000000L // CG_VCEPLL_FUNC_CNTL_2 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_A_MASK 0x0000007fL #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_B_MASK 0x00007f00L #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_LEGACY_PDIV_MASK 0x00020000L #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_FASTEN_MASK 0x00040000L #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_ENSAT_MASK 0x00080000L #define CG_VCEPLL_FUNC_CNTL_2__EVCLK_SRC_SEL_MASK 0x01f00000L #define CG_VCEPLL_FUNC_CNTL_2__ECCLK_SRC_SEL_MASK 0x3e000000L #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_TEST_MASK 0x40000000L #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_UNLOCK_CLEAR_MASK 0x80000000L // CG_VCEPLL_FUNC_CNTL_3 #define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_FB_DIV_MASK 0x03ffffffL #define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_DITHEN_MASK 0x10000000L // CG_VCEPLL_FUNC_CNTL_4 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_TEST_SEL_MASK 0x00000007L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT_SEL_MASK 0x00000030L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EN_MASK 0x000000c0L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE_MASK 0x0003ff00L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_REG_BIAS_MASK 0x001c0000L #define CG_VCEPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x00200000L #define CG_VCEPLL_FUNC_CNTL_4__BG_PDN_MASK 0x00400000L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_ILOCK_MASK 0x00800000L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_FBCLK_SEL_MASK 0x01000000L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VCTRLADC_EN_MASK 0x02000000L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT_MASK 0x0c000000L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE_EXT_MASK 0x70000000L #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VTOI_BIAS_CNTL_MASK 0x80000000L // CG_VCEPLL_FUNC_CNTL_5 #define CG_VCEPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x00000001L #define CG_VCEPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x00000002L #define CG_VCEPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0x0000000cL #define CG_VCEPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x00000030L #define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0x000000c0L #define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x00000100L #define CG_VCEPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x00000200L // CG_VCEPLL_STATUS #define CG_VCEPLL_STATUS__VCEPLL_CTLACK_A_MASK 0x00000001L #define CG_VCEPLL_STATUS__VCEPLL_CTLACK_B_MASK 0x00000002L #define CG_VCEPLL_STATUS__VCEPLL_CLKF_ACK_MASK 0x00000004L #define CG_VCEPLL_STATUS__VCEPLL_CLKR_ACK_MASK 0x00000008L #define CG_VCEPLL_STATUS__VCEPLL_VCTRLADC_MASK 0x000000f0L #define CG_VCEPLL_STATUS__VCEPLL_OSPARE_MASK 0x00000f00L #define CG_VCEPLL_STATUS__VCEPLL_INTRESET_MASK 0x00001000L #define CG_VCEPLL_STATUS__VCEPLL_UNLOCK_MASK 0x00010000L #define CG_VCEPLL_STATUS__VCEPLL_UNLOCK_STICKY_MASK 0x00020000L // CG_VCEPLL_SPREAD_SPECTRUM #define CG_VCEPLL_SPREAD_SPECTRUM__SSEN_MASK 0x00000003L #define CG_VCEPLL_SPREAD_SPECTRUM__SPARE_MASK 0x0000000cL #define CG_VCEPLL_SPREAD_SPECTRUM__CLKS_MASK 0x0000fff0L #define CG_VCEPLL_SPREAD_SPECTRUM__BWADJ_MASK 0x0fff0000L // CG_VCEPLL_SPREAD_SPECTRUM_2 #define CG_VCEPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x03ffffffL // CG_VCEPLL_FUNC_CNTL #define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET__SHIFT 0x00000000 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_SLEEP__SHIFT 0x00000001 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_BYPASS_EN__SHIFT 0x00000002 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLREQ__SHIFT 0x00000003 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_REFCLK_SEL__SHIFT 0x00000004 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKF_UPDATE__SHIFT 0x00000006 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CLKR_UPDATE__SHIFT 0x00000007 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_RESET_EN__SHIFT 0x00000008 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_VCO_MODE__SHIFT 0x00000009 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_REF_DIV__SHIFT 0x00000010 #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK__SHIFT 0x0000001e #define CG_VCEPLL_FUNC_CNTL__VCEPLL_CTLACK2__SHIFT 0x0000001f // CG_VCEPLL_FUNC_CNTL_2 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_A__SHIFT 0x00000000 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_PDIV_B__SHIFT 0x00000008 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_LEGACY_PDIV__SHIFT 0x00000011 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_FASTEN__SHIFT 0x00000012 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_ENSAT__SHIFT 0x00000013 #define CG_VCEPLL_FUNC_CNTL_2__EVCLK_SRC_SEL__SHIFT 0x00000014 #define CG_VCEPLL_FUNC_CNTL_2__ECCLK_SRC_SEL__SHIFT 0x00000019 #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_TEST__SHIFT 0x0000001e #define CG_VCEPLL_FUNC_CNTL_2__VCEPLL_UNLOCK_CLEAR__SHIFT 0x0000001f // CG_VCEPLL_FUNC_CNTL_3 #define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_FB_DIV__SHIFT 0x00000000 #define CG_VCEPLL_FUNC_CNTL_3__VCEPLL_DITHEN__SHIFT 0x0000001c // CG_VCEPLL_FUNC_CNTL_4 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_TEST_SEL__SHIFT 0x00000000 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT_SEL__SHIFT 0x00000004 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EN__SHIFT 0x00000006 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE__SHIFT 0x00000008 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_REG_BIAS__SHIFT 0x00000012 #define CG_VCEPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x00000015 #define CG_VCEPLL_FUNC_CNTL_4__BG_PDN__SHIFT 0x00000016 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_ILOCK__SHIFT 0x00000017 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_FBCLK_SEL__SHIFT 0x00000018 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VCTRLADC_EN__SHIFT 0x00000019 #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SCLK_EXT__SHIFT 0x0000001a #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_SPARE_EXT__SHIFT 0x0000001c #define CG_VCEPLL_FUNC_CNTL_4__VCEPLL_VTOI_BIAS_CNTL__SHIFT 0x0000001f // CG_VCEPLL_FUNC_CNTL_5 #define CG_VCEPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x00000000 #define CG_VCEPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x00000001 #define CG_VCEPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x00000002 #define CG_VCEPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x00000004 #define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x00000006 #define CG_VCEPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x00000008 #define CG_VCEPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x00000009 // CG_VCEPLL_STATUS #define CG_VCEPLL_STATUS__VCEPLL_CTLACK_A__SHIFT 0x00000000 #define CG_VCEPLL_STATUS__VCEPLL_CTLACK_B__SHIFT 0x00000001 #define CG_VCEPLL_STATUS__VCEPLL_CLKF_ACK__SHIFT 0x00000002 #define CG_VCEPLL_STATUS__VCEPLL_CLKR_ACK__SHIFT 0x00000003 #define CG_VCEPLL_STATUS__VCEPLL_VCTRLADC__SHIFT 0x00000004 #define CG_VCEPLL_STATUS__VCEPLL_OSPARE__SHIFT 0x00000008 #define CG_VCEPLL_STATUS__VCEPLL_INTRESET__SHIFT 0x0000000c #define CG_VCEPLL_STATUS__VCEPLL_UNLOCK__SHIFT 0x00000010 #define CG_VCEPLL_STATUS__VCEPLL_UNLOCK_STICKY__SHIFT 0x00000011 // CG_VCEPLL_SPREAD_SPECTRUM #define CG_VCEPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x00000000 #define CG_VCEPLL_SPREAD_SPECTRUM__SPARE__SHIFT 0x00000002 #define CG_VCEPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x00000004 #define CG_VCEPLL_SPREAD_SPECTRUM__BWADJ__SHIFT 0x00000010 // CG_VCEPLL_SPREAD_SPECTRUM_2 #define CG_VCEPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x00000000 > > Regards, > Christian. > > > > > Signed-off-by: Timur Kristóf <[email protected]> > > --- > > drivers/gpu/drm/amd/amdgpu/si.c | 6 +----- > > drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 10 +++++++++- > > 2 files changed, 10 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/si.c > > b/drivers/gpu/drm/amd/amdgpu/si.c index f7b35b860ba3..ed3d4f9bf9d9 > > 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/si.c > > +++ b/drivers/gpu/drm/amd/amdgpu/si.c > > @@ -1902,7 +1902,7 @@ static int si_vce_send_vcepll_ctlreq(struct > amdgpu_device *adev) > > WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, > ~UPLL_CTLREQ_MASK); > > > > if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) { > > - DRM_ERROR("Timeout setting VCE clocks!\n"); > > + DRM_WARN("Timeout setting VCE clocks!\n"); > > return -ETIMEDOUT; > > } > > > > @@ -1954,8 +1954,6 @@ static int si_set_vce_clocks(struct amdgpu_device > *adev, u32 evclk, u32 ecclk) > > mdelay(1); > > > > r = si_vce_send_vcepll_ctlreq(adev); > > - if (r) > > - return r; > > > > /* Assert VCEPLL_RESET again */ > > WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, > > ~VCEPLL_RESET_MASK); @@ -1988,8 +1986,6 @@ static int > si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) > > WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, > ~VCEPLL_BYPASS_EN_MASK); > > > > r = si_vce_send_vcepll_ctlreq(adev); > > - if (r) > > - return r; > > > > /* Switch VCLK and DCLK selection */ > > WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > index 27f70146293d..fdc455797258 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > @@ -401,7 +401,7 @@ static int vce_v1_0_wait_for_idle(struct > > amdgpu_ip_block *ip_block) static int vce_v1_0_start(struct > > amdgpu_device *adev) { > > struct amdgpu_ring *ring; > > - int r; > > + int r, i; > > > > WREG32_P(mmVCE_STATUS, 1, ~1); > > > > @@ -443,6 +443,14 @@ static int vce_v1_0_start(struct amdgpu_device *adev) > > /* Clear VCE_STATUS, otherwise SRBM thinks VCE1 is busy. */ > > WREG32(mmVCE_STATUS, 0); > > > > + /* Wait for VCE_STATUS to actually clear. > > + * This helps when there was a timeout setting the VCE clocks. > > + */ > > + for (i = 0; i < adev->usec_timeout && RREG32(mmVCE_STATUS); ++i) { > > + udelay(1); > > + WREG32(mmVCE_STATUS, 0); > > + } > > + > > if (r) { > > dev_err(adev->dev, "VCE not responding, giving up!!!\n"); > > return r;
