Need to make sure gfxoff is disallowed when we touch GC registers over MMIO.
Cc: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 496121bdc1de1..31dd0aeef509d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9141,6 +9141,7 @@ static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, unsigned int type, enum amdgpu_interrupt_state state) { + amdgpu_gfx_off_ctrl(adev, false); switch (type) { case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); @@ -9175,6 +9176,8 @@ static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -9226,6 +9229,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -9260,6 +9264,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -9272,6 +9277,7 @@ static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -9306,6 +9312,8 @@ static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } @@ -9317,6 +9325,7 @@ static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, u32 cp_int_cntl_reg, cp_int_cntl; int i, j; + amdgpu_gfx_off_ctrl(adev, false); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: case AMDGPU_IRQ_STATE_ENABLE: @@ -9337,6 +9346,7 @@ static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -9410,6 +9420,7 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, uint32_t tmp, target; struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); + amdgpu_gfx_off_ctrl(adev, false); if (ring->me == 1) target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); else @@ -9444,6 +9455,8 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, BUG(); /* kiq only support GENERIC2_INT now */ break; } + amdgpu_gfx_off_ctrl(adev, true); + return 0; } -- 2.52.0
