Need to make sure gfxoff is disallowed when we touch GC registers over MMIO.
Cc: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 2519bdf4d109e..8116625c92d92 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -3575,6 +3575,7 @@ static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, { int i, num_xcc; + amdgpu_gfx_off_ctrl(adev, false); num_xcc = NUM_XCC(adev->gfx.xcc_mask); for (i = 0; i < num_xcc; i++) { switch (type) { @@ -3598,6 +3599,7 @@ static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, break; } } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -3668,6 +3670,7 @@ static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, { int i, num_xcc; + amdgpu_gfx_off_ctrl(adev, false); num_xcc = NUM_XCC(adev->gfx.xcc_mask); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: @@ -3680,6 +3683,7 @@ static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } @@ -3691,6 +3695,7 @@ static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, { int i, num_xcc; + amdgpu_gfx_off_ctrl(adev, false); num_xcc = NUM_XCC(adev->gfx.xcc_mask); switch (state) { case AMDGPU_IRQ_STATE_DISABLE: @@ -3703,6 +3708,7 @@ static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, default: break; } + amdgpu_gfx_off_ctrl(adev, true); return 0; } -- 2.52.0
