Ping on this series?
On Fri, Jun 26, 2026 at 4:49 PM Alex Deucher <[email protected]> wrote: > > This is needed to allocate occlusion counters across > both gfx pipes. > > Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support") > Signed-off-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index d72ecf5dab09e..6ff7a8a700939 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct > amdgpu_device *adev) > gfx_v10_0_get_tcc_info(adev); > adev->gfx.config.pa_sc_tile_steering_override = > gfx_v10_0_init_pa_sc_tile_steering_override(adev); > + /* program DB_RING_CONTROL for multiple GFX pipes */ > + WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, > + (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); > > /* XXX SH_MEM regs */ > /* where to put LDS, scratch, GPUVM in FSA64 space */ > -- > 2.54.0 >
