On Tuesday, July 7, 2026 3:44:28 PM Central European Summer Time Alex Deucher wrote: > On Tue, Jul 7, 2026 at 4:06 AM Timur Kristóf <[email protected]> wrote: > > On 2026. június 26., péntek 22:40:58 közép-európai nyári idő Alex Deucher > > > > wrote: > > > This is needed to allocate occlusion counters across > > > both gfx pipes. > > > > > > Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support") > > > Signed-off-by: Alex Deucher <[email protected]> > > > --- > > > > > > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > > > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index > > > d72ecf5dab09e..6ff7a8a700939 > > > 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > > > @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct > > > amdgpu_device *adev) gfx_v10_0_get_tcc_info(adev); > > > > > > adev->gfx.config.pa_sc_tile_steering_override = > > > > > > gfx_v10_0_init_pa_sc_tile_steering_override(adev); > > > > > > + /* program DB_RING_CONTROL for multiple GFX pipes */ > > > + WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, > > > + (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); > > > > Hi Alex, > > > > Why do you set this to zero when the number of pipes is more than 1? > > Wouldn't it need to be the other way around and set to the number of pipes > > (or number of rings)? > > The hardware default is 1. The other settings are as follows for this > field: 0 - split occlusion counters between gfx pipes > 1 - all occlusion counters to pipe 0 > 2 - all occlusion counters to pipe 1 >
I see, thanks! Could you please mention that in a comment or maybe add an enum for the possible values of that field? With that, the series is: Reviewed-by: Timur Kristóf <[email protected]> > > > > > /* XXX SH_MEM regs */ > > > /* where to put LDS, scratch, GPUVM in FSA64 space */
