[PATCH 11/12] drm/amd/display: interface to obtain minimum plane size caps

[Qingqing Zhuo]

From: Igor Kravchenko <igor.kravche...@amd.com>

[Why]
Implement an interface to obtain plane size caps

[How]
Add min_width, min_height fields to dc_plane_cap structure.
Set values to 16x16 for discrete ASICs, and 64x64 for others.

Signed-off-by: Igor Kravchenko <igor.kravche...@amd.com>
Reviewed-by: Aric Cyr <aric....@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h                     | 3 +++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 8 ++++++--
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 4 +++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 4 +++-
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c   | 4 +++-
 5 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index e5a1a9eb6217..a5faedf66470 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -96,6 +96,9 @@ struct dc_plane_cap {
                uint32_t nv12;
                uint32_t fp16;
        } max_downscale_factor;
+       // minimal width/height
+       uint32_t min_width;
+       uint32_t min_height;
 };
 
 // Color management caps (DPP and MPC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index a043ddae5149..70c6f917139e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -423,7 +423,9 @@ static const struct dc_plane_cap plane_cap = {
                                .argb8888 = 250,
                                .nv12 = 1,
                                .fp16 = 1
-               }
+               },
+               64,
+               64
 };
 
 static const struct dc_plane_cap underlay_plane_cap = {
@@ -447,7 +449,9 @@ static const struct dc_plane_cap underlay_plane_cap = {
                                .argb8888 = 1,
                                .nv12 = 250,
                                .fp16 = 1
-               }
+               },
+               64,
+               64
 };
 
 #define CTX  ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 51b3fe502670..5d83e8174005 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -424,7 +424,9 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = 250,
                        .nv12 = 1,
                        .fp16 = 1
-       }
+       },
+       64,
+       64
 };
 
 #define CTX  ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c8c6225c7e9e..968a89bbcf24 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1043,7 +1043,9 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = 250,
                        .nv12 = 250,
                        .fp16 = 1
-       }
+       },
+       16,
+       16
 };
 static const struct resource_caps res_cap_nv14 = {
                .num_timing_generator = 5,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7d82648bec90..88d41a385add 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -857,7 +857,9 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = 250,
                        .nv12 = 250,
                        .fp16 = 250
-       }
+       },
+       64,
+       64
 };
 
 static const struct dc_debug_options debug_defaults_drv = {
-- 
2.17.1

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