From: Reza Amini <reza.am...@amd.com>
[Why]
To support V3
[How]
Generate new VSIF for V3
Signed-off-by: Reza Amini <reza.am...@amd.com>
Reviewed-by: Anthony Koo <anthony....@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 19 +++++++++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 ++++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 6 +++
.../amd/display/modules/freesync/freesync.c | 41 +++++++++++++++++++
4 files changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index d6989d115c5c..41c278519b67 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -244,6 +244,25 @@ struct dc_stream_status *dc_stream_get_status(
return dc_stream_get_status_from_state(dc->current_state, stream);
}
+#ifndef TRIM_FSFT
+/**
+ * dc_optimize_timing() - dc to optimize timing
+ */
+bool dc_optimize_timing(
+ struct dc_crtc_timing *timing,
+ unsigned int max_input_rate_in_khz)
+{
+ //optimization is expected to assing a value to these:
+ //timing->pix_clk_100hz
+ //timing->v_front_porch
+ //timing->v_total
+ //timing->fast_transport_output_rate_100hz;
+ timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
+
+ return true;
+}
+#endif
+
/**
* dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor
surface address
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index b7a8c71e3e39..1a87bc3da826 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -713,6 +713,9 @@ struct dc_crtc_timing_flags {
uint32_t LTE_340MCSC_SCRAMBLE:1;
uint32_t DSC : 1; /* Use DSC with this timing */
+#ifndef TRIM_FSFT
+ uint32_t FAST_TRANSPORT: 1;
+#endif
};
enum dc_timing_3d_format {
@@ -772,6 +775,10 @@ struct dc_crtc_timing {
enum dc_aspect_ratio aspect_ratio;
enum scanning_type scan_type;
+#ifndef TRIM_FSFT
+ uint32_t fast_transport_output_rate_100hz;
+#endif
+
struct dc_crtc_timing_flags flags;
struct dc_dsc_config dsc_cfg;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index f2ed9bc5a319..f599a72dab50 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -419,6 +419,12 @@ struct dc_stream_status *dc_stream_get_status_from_state(
struct dc_stream_status *dc_stream_get_status(
struct dc_stream_state *dc_stream);
+#ifndef TRIM_FSFT
+bool dc_optimize_timing(
+ struct dc_crtc_timing *timing,
+ unsigned int max_input_rate_in_khz);
+#endif
+
/*******************************************************************************
* Cursor interfaces - To manages the cursor within a stream
******************************************************************************/
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index d3a5ba9ee782..7a2500fbf3f2 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -760,9 +760,35 @@ static void build_vrr_infopacket_v2(enum signal_type
signal,
infopacket->valid = true;
}
+#ifndef TRIM_FSFT
+static void build_vrr_infopacket_fast_transport_data(
+ bool ftActive,
+ unsigned int ftOutputRate,
+ struct dc_info_packet *infopacket)
+{
+ /* PB9 : bit7 - fast transport Active*/
+ unsigned char activeBit = (ftActive) ? 1 << 7 : 0;
+
+ infopacket->sb[1] &= ~activeBit; //clear bit
+ infopacket->sb[1] |= activeBit; //set bit
+
+ /* PB13 : Target Output Pixel Rate [kHz] - bits 7:0 */
+ infopacket->sb[13] = ftOutputRate & 0xFF;
+
+ /* PB14 : Target Output Pixel Rate [kHz] - bits 15:8 */
+ infopacket->sb[14] = (ftOutputRate >> 8) & 0xFF;
+
+ /* PB15 : Target Output Pixel Rate [kHz] - bits 23:16 */
+ infopacket->sb[15] = (ftOutputRate >> 16) & 0xFF;
+
+}
+#endif
static void build_vrr_infopacket_v3(enum signal_type signal,
const struct mod_vrr_params *vrr,
+#ifndef TRIM_FSFT
+ bool ftActive, unsigned int ftOutputRate,
+#endif
enum color_transfer_func app_tf,
struct dc_info_packet *infopacket)
{
@@ -773,6 +799,13 @@ static void build_vrr_infopacket_v3(enum signal_type
signal,
build_vrr_infopacket_fs2_data(app_tf, infopacket);
+#ifndef TRIM_FSFT
+ build_vrr_infopacket_fast_transport_data(
+ ftActive,
+ ftOutputRate,
+ infopacket);
+#endif
+
build_vrr_infopacket_checksum(&payload_size, infopacket);
infopacket->valid = true;
@@ -795,7 +828,15 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync
*mod_freesync,
switch (packet_type) {
case PACKET_TYPE_FS_V3:
+#ifndef TRIM_FSFT
+ build_vrr_infopacket_v3(
+ stream->signal, vrr,
+ stream->timing.flags.FAST_TRANSPORT,
+ stream->timing.fast_transport_output_rate_100hz,
+ app_tf, infopacket);
+#else
build_vrr_infopacket_v3(stream->signal, vrr, app_tf,
infopacket);
+#endif
break;
case PACKET_TYPE_FS_V2:
build_vrr_infopacket_v2(stream->signal, vrr, app_tf,
infopacket);
--
2.17.1
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