Hi, On 10/15/2014 11:34 PM, Slichter, Daniel H. wrote: > I agree with Robert that DMA would be the most sensible next step > here, rather than trying other tweaks. I don't really know how > difficult this would be to implement, though.
Implementing DMA in the SoC is not necessarily very difficult depending on how it is to be done. Most of the issues revolve around having a consistent software/user interface for DMA RTIO and for non-DMA RTIO. We also need to keep in mind that other devices may need to be controlled in the middle of a series of RTIO pulses (e.g. the DDS data bus). If we go the DMA route, maybe a good option is to have DRAM backing of the RTIO FIFOs that is implemented all in gateware and is fully transparent for the software. Then we can have FIFOs with hundreds of megabytes of storage (note that loading/unloading them will take some time). But this is not straightforward to do, and wasting the abundance of resources that the K7 FPGA has on large on-chip FIFO memories is much easier. > It would be a handy > feature if one wanted to stream pre-programmed data to a high speed > DAC, for example, or record data points from a high speed ADC -- > useful if one is interested in implementing the kind of extensible > hardware Joe has championed. Yes; that DMA-capable DAC/ADC would be another device from the software point of view (if not another physical device). > Right now, the > longest patterns are limited by the depth of the FIFO queue for each > RTIO (real-time input/output) channel, which is 64 entries deep per > channel (Sebastien, can this be made deeper on the KC705?). Yes. > I think it's safe to say that we might want timestamps as well as > counts, so would it be possible to make one or two input channels > with very deep FIFOs, and the rest with standard ones? Yes. Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
