On 10/17/2014 07:50 AM, Slichter, Daniel H. wrote: > For your experiments 1 and 2 the count rate is ~1 MHz and so the > processor will probably not be able to read all the events out of the > queue as fast as they come in.
1 MHz does not sound like an unreasonable performance target for software and RTIO/processor communication optimizations. And we can have the large block RAM FIFO as you said, as a plan B that is easy to roll out. > Sebastien, how does the RTIO core handle overflow of the FIFO queue > for inputs? With the current code, events that cannot be put into the FIFO because it is full are silently discarded. I can have the RTIO driver raise an exception in those cases. I propose that the exception be raised when the user attempts to read from an input FIFO that has overflown. The FIFO can also be disabled when the RTIO input is in gateware counter mode (and no overflow exceptions will be raised in this mode). Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
