> 1 MHz does not sound like an unreasonable performance target for software > and RTIO/processor communication optimizations. And we can have the > large block RAM FIFO as you said, as a plan B that is easy to roll out.
If you think this is doable, then please go ahead with the further optimizations necessary. I think it would be nice to have the option of the large block RAM FIFO with user-selectable depth (at bitstream compile time) anyway, since it sounds not too hard to implement. > With the current code, events that cannot be put into the FIFO because it is > full are silently discarded. I can have the RTIO driver raise an exception in > those cases. I propose that the exception be raised when the user attempts > to read from an input FIFO that has overflown. Sounds good. > The FIFO can also be disabled when the RTIO input is in gateware counter > mode (and no overflow exceptions will be raised in this mode). Sounds good. Daniel _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
