> When would the binder and > loader have something to do here? If CSECT A wants to call a routine in CSECT B, why should it be restricted to using an instruction with a base register? If the binder knows that CSECT A begins at, say, x'1000' into the resulting load module and CSECT B begins at x'5000', the relative displacement of the instruction and the target is easy for the binder to calculate. (If CSECT A and CSECT B are in different load modules then the situation is obviously different.) Also, there's no relocation for the loader to do, assuming the entire load module is loaded as a single unit, because simply loading the module at a different address won't cause the relative displacements to change.
> But if the code was not generated by the assembler, a > relative branch could well be a wild branch. The hardware has not > means of verifying the offset is "good", it just adds the value, right? Do you consider this "generated by the assembler"? Maybe not strictly, but it's generated by the assembler and binder working together. And there are certainly ways for register-based targets to be wild branches, too. The relative-branch instructions may in fact be safer since they avoid the many possible ways a base register can be corrupted. Either the binder knows where the instruction and the target are relative to each other, or else it can't figure it out and informs the user that it failed to resolve the reference. Once resolved, the only way for the relative-branch instruction to *not* execute correctly is if someone relocates the instruction but not the target, or vice versa. Appendix B in the HLASM Programmer's Guide describes the RLD format for 2-byte and 4-byte relative displacements. - mb > From: Peter Hunkeler <[email protected]> > To: [email protected] > Date: 12/17/2015 06:29 AM > Subject: AW: Re: Reltive branches to outside a control section > Sent by: IBM Mainframe Assembler List <[email protected]> > > > program will be loaded at run time. While it is possible to generate a > > relative-branch relocation entry in the ESD, I'm not aware of any > > facility to have the Binder and IEWFETCH resolve this offset to a > > fixed low-storage address at run time. > > > > Pardon my ignorance, but I baffled by the fact there might be an ESD > entry related to a relative branch. I understood the relative brach > to brach to an address offset from the current instructions address > by the specified number of halfwords. When would the binder and > loader have something to do here? > > > I had not given thought to it before, but it was mentioned in this > thread that the assembler would inhibit relative branch outside of > the CSECT. But if the code was not generated by the assembler, a > relative branch could well be a wild branch. The hardware has not > means of verifying the offset is "good", it just adds the value, right? > > > What am I missing? A pointer to some FM to read is sufficient. > > > -- > Peter Hunkeler > > > > > >
