Yes, and an even better answer.

Thanks,
Robert Ngan
HCL Technologies

-----Original Message-----
From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> On Behalf 
Of Jim Mulder
Sent: Friday, November 1, 2019 10:42
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Vector enablement control?

  The question you really want to ask is "how should I determine if the  task 
under which I am running has used already used vector instructions"?

  The answer is to look at  PSAVSS or STCBVSS (which are classified as 
Programming Interfaces).

Jim Mulder z/OS Diagnosis, Design, Development, Test  IBM Corp.
Poughkeepsie NY

"IBM Mainframe Assembler List" <ASSEMBLER-LIST@LISTSERV.UGA.EDU> wrote on
10/31/2019 01:30:13 PM:

> From: "Ngan, Robert" <rn...@dxc.com>
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date: 11/01/2019 11:36 AM
> Subject: Vector enablement control?
> Sent by: "IBM Mainframe Assembler List"
<ASSEMBLER-LIST@LISTSERV.UGA.EDU>
>
> With the new COBOL compilers capable of generating vector instructions
> for handling packed fields, I'm looking at modifying our ESTAE
> routines to dump the contents of the vector registers.
> The PoOPs says you should not issue a vector instruction unless both
> the vector enablement control and AFP-register control bits in CR0 are
on.
> If you're running z/OS on a z13 of higher (i.e. your machine a vector
> instruction support), would either of these two bits ever be off?
>
> From a standard ESTAE routine, I can examine the CR0 contents from the
> SDWA, but in a CICS ABEND exit, I don't have access to CR0.
>
> Robert Ngan
> HCL Technologies

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