From memories of 30-ish years ago...
I worked on MDF (Multiple Domain Facility -- What IBM came to
call PR/SM and domains got called LPARs) at Amdahl.
So let me elaborate on what Seymour said just based on the Amdahl
MVS Structure and Flow class I had (2 weeks of in depth teaching).
When you hit the blue LOAD button (as I recall that was the
color), the system went into IPL mode/state (I've forgotten which
is the formal name) and fetched from a specific volume the IPL TEXT.
Now we summarize all the fun from that.
Page Frame 0 for that DOMAIN/LPAR is *the INITIAL* PSA (PSA 0)
while in IPL mode/state. This is all done in REAL mode. So you
get all of the IRIM and RIMs done (Initial Resource
Initialization Module, and Resource INIT module -- I didn't come
up with those names, IBM did) and you are now preparing for MP
INIT (or DP if you only have a Dyadic machine), so, you point
some register (not 0) at this PSA you are about to build, doing a
copy from the PSA 0 to this PSA being built and now you load your
prefix reg with this address. Now R0 is pointing to this new PSA
and no longer to PSA 0.
Why did we do this? Because PSA 0 now has all of the NEW/PSWs set
to point to the xxx Interrupt FLIHs (First Level Interrupt
Handlers). And it has all the other stuff that has to be anchored
in the PSA stored at the specified positions.
I have forgotten when RSM (Real Storage Manager) has been done,
and VSM, etc. are init-ed, but DAT should now be active.
We can now do "MP" INIT. For each CPU we have to get the storage
for its PSA and copy PSA 0 to it to init it -- You may need to
make a change in that PSA, so you have to address it with
something other than R0. Once that is done, a SIGP RESTART is
done for that CPU. Now that CPU goes through all the stuff it
must to get to a dispatchable state for the dispatcher to control
it. And that may be a very short # of items.
Rinse repeat for each CPU defined for this domain/LPAR.
That's one use of addressing a PSA where you can't use R0.
ACR -- Alternate CPU recovery may be another.
MCK -- Machine check handler. It may have to look at a dead CPU
(MCK PD comes to mind, and PI loop is another -- but that may be
done in ACR) and so it has to use something other than R0 to look
at that processor's PSA.
Now you know some of the reasons for using other than R0 to
address a PSA.
Again, it has been 30 years now since I worked at that level and
MVS has changed a lot since then.
Regards,
Steve Thompson
On 11/12/19 2:01 PM, Seymour J Metz wrote:
No, it's not a waste of resources. There is a valid use case regardless of
whether you can conceive of it.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
________________________________________
From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> on behalf of
John McKown <john.archie.mck...@gmail.com>
Sent: Tuesday, November 12, 2019 8:13 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Questionable Instructions in Obtaining EAX documentation
On Tue, Nov 12, 2019 at 6:56 AM Peter Relson <rel...@us.ibm.com> wrote:
<snip>
What if R9 is not supposed to be zero? Maybe the code is looking at the
PSA
of another processor.
</snip>
The normal way to accomplish that is
USING PSA,R9
rather than leaving a time-bomb for those who come after by using "0".
I cannot fathom the reason to use _any_ base for the PSA other than GPR0.
It is simply wasteful of a scarce resource.
Peter Relson
z/OS Core Technology Design
--
People in sleeping bags are the soft tacos of the bear world.
Maranatha! <><
John McKown
