OK. Let's go through the code one instruction at a time.
I1 LLGC R0,BYTE Low order byte of R0 * contains byte of interest. * * Bits 56-59 contain the two * adjacent bit pairs of * interest. * * Bits 60-63 are of no * interest. * * Bits 0-55 are zero. * I2 SRL R0,4(0) Bits 60-63 of R0 contain * the pair of two bits of * interest. Bits 0-59 are * zero. * I3 SRLG R1,R0,2(0) R1 contains the first pair * of bits of interest in bits * 62-63. Bits 0-61 are zero. * I4 NILL R0,B'11' R0 contains the second pair * of bits of interest in bits * 62-63. Bits 0-61 are zero. * I5 AHI R0,C'1' * Convert the bit pairs to I6 AHI R1,C'1' * Zoned Decimal format, * * origined at 1. In the commentary below I will show the bytes of a register as two hex digits per byte, with bytes separated by underscore characters. When showing the bits of a byte, all eight bits will be shown. The bits of the BYTE data item are laid out as follows: JKYZxxxx Where the leftmost two bits (JK) are the first bit pair of interest, and the next two bits (YZ) are the next pair of bits of interest. The remaining four bits (xxxx) are of no interest. Instruction I1 At the completion of this instruction the 64-bit GPR 0 contains: 00_00_00_00_00_00_00_JKYZxxxx Instruction I2 This shifts the low order 32-bits of the 64-bit GPR 0 right by four bits. The High order 32-bits of the 64-bit GPR 0 are unchanged. At the completion of this instruction the 64-bit GPR 0 contains: 00_00_00_00_00_00_00_0000JKYZ Instruction I3 This shifts the CONTENT of the 64-bit GPR 0 (not the register itself) right by two bits and places the 64-bit result of the shift into the 64-bit GPR 1. GPR 0 is UNCHANGED by this operation. At the completion of this instruction, the 64-bit GPRs of interest contain: GPR 0: 00_00_00_00_00_00_00_0000JKYZ GPR 1: 00_00_00_00_00_00_00_000000JK Instruction I4 This performs a bitwise AND of the rightmost 16-bits of the 64-bit GPR 0 with the immediate operand of B'00000011'. The leftmost 48-bits of the 64-bit GPR 0 are unchanged by this operation. At the completion of this instruction, the 64-bit GPRs of interest contain: GPR 0: 00_00_00_00_00_00_00_000000YZ GPR 1: 00_00_00_00_00_00_00_000000JK Instruction I5 This performs a Signed Add of the Signed immediate operand value of x'00F1' to the low order 32-bits of the 64-bit GPR 0. Note that a Fixed-Point Overflow cannot occur. The maximum value which can result from the Addition is 00_00_00_F4. The low order 32-bits of the 64-bit GPR 0 are replaced by the resultant sum. The high order 32-bits of the 64-bit GPR 0 are unchanged by this operation. Instruction I6 This performs the identical operation as instruction I5, except the 64-bit GPR being operated upon is Register 1 instead of Register 0.
