"IBM Mainframe Assembler List" <ASSEMBLER-LIST@LISTSERV.UGA.EDU> wrote on 02/05/2022 08:25:37 AM: > The lowest-tech approach using only two regs (no 64-bit regs, no z/Arch > instructions, no 6-byte instructions even) that came to mind was this: > > ICM 0,B'1000',BYTE Put the byte into bits 0-7 > SRDL 0,30 Move BYTE.0-1 to reg 0.30-31, > * zeroing reg 0.0-29 > * BYTE.2-3 to reg 1.0-1 > SRL 1,30 Move BYTE.2-3 to reg 1.30-31, > * zeroing reg 1.0-29 > AHI 0,C'1' 0-3 => C'1'-C'4' > AHI 1,C'1' > STC 0,target0 > STC 1,target1 > BYTE DS X > > I.e., taking advantage of needing to do a shift anyway to avoid having to > clear anything.
I like that one and it is easy to understand what it is doing. I will keep that one. Thanks. Sincerely, Dave Clark -- int.ext: 91078 direct: (937) 531-6378 home: (937) 751-3300 Winsupply Group Services 3110 Kettering Boulevard Dayton, Ohio 45439 USA (937) 294-5331 ********************************************************************************************* This email message and any attachments is for use only by the named addressee(s) and may contain confidential, privileged and/or proprietary information. If you have received this message in error, please immediately notify the sender and delete and destroy the message and all copies. All unauthorized direct or indirect use or disclosure of this message is strictly prohibited. No right to confidentiality or privilege is waived or lost by any error in transmission. *********************************************************************************************