On Wed, Nov 04, 2009 at 01:52:30PM -0800, Luis R. Rodriguez wrote: > > Even better: I just confirmation from our systems team that our legacy > > devices and 11n PCI devices don't support MWR so I'll remove all that > > cruft crap. > > I meant MWI of course.
Yes, but they don't necessarily just use cacheline size for MWI ... some devices use cacheline size for setting up data structures. Might be worth just checking explicitly that they don't use the cacheline size register for anything. -- Matthew Wilcox Intel Open Source Technology Centre "Bill, look, we understand that you're interested in selling us this operating system, but compare it to ours. We can't possibly take such a retrograde step." _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
