2009/11/5 Luis R. Rodriguez <mcg...@bombadil.infradead.org>: > On Wed, Nov 04, 2009 at 02:04:11PM -0800, Luis R. Rodriguez wrote: >> On Wed, Nov 4, 2009 at 2:00 PM, Matthew Wilcox <matt...@wil.cx> wrote: >> > On Wed, Nov 04, 2009 at 01:52:30PM -0800, Luis R. Rodriguez wrote: >> >> > Even better: I just confirmation from our systems team that our legacy >> >> > devices and 11n PCI devices don't support MWR so I'll remove all that >> >> > cruft crap. >> >> >> >> I meant MWI of course. >> > >> > Yes, but they don't necessarily just use cacheline size for MWI ... some >> > devices use cacheline size for setting up data structures. Might be >> > worth just checking explicitly that they don't use the cacheline size >> > register for anything. >> >> Oh right -- so the typical Atheros hack for this is to check the cache >> line size, and if its 0 set it to L1_CACHE_BYTES. Then eventually read >> from PCI_CACHE_LINE_SIZE pci config to align the skb data. So what I >> was doing now is removing all this cruft and replacing it with a >> generic allocator for atheros drivers that aligns simply to the >> L1_CACHE_BYTES. Sound kosher? > > Something like this: >
According to comments inside MadWiFi AR5210 needs cache line align else we get corruptions. I don't know if this is correct for all platforms or later cards but since we (plan to) support AR5210 i guess we should leave it there. We need to test this a lot on various archs/cards before applying it. -- GPG ID: 0xD21DB2DB As you read this post global entropy rises. Have Fun ;-) Nick _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
