P Floding;184744 Wrote: > Did you read AndyC_772's postings? > He explains that the way SPDIF works makes it impossible to have the > master clock at the DAC, and hence the amount of interface jitter > rejection is implementation dependent. Which is how it is. > > I'd ask all engineering types who think they know things without > actually reading up on the subject to please go and read up first. > (And, yes, I am an EE too, AND an audiophile. And, no, I don't believe > in alternative woodoo laws of physics, nor do I believe we now got it > all figured out and can lay back and stop questioning.) (General > comment, not directed at you opaqueice!) > > Best regards
Yes but...it is entirely possible to "remodel" the clock at the DAC input (ie right on the SPDIF socket) - see here http://www.altmann.haan.de/jitter/english/engc_navfr.html -- Phil Leigh ------------------------------------------------------------------------ Phil Leigh's Profile: http://forums.slimdevices.com/member.php?userid=85 View this thread: http://forums.slimdevices.com/showthread.php?t=33146 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
