Well, I read 'em both. Yeah, not much mention of that, but I can conclude (with a high degree of certainty) that both refer to *word clock*. IOW, 44.1 kHz. If you look closely at the first paper, they point out that everyone could hear 2 uSec of jitter. You simply can not make a 256 Fs clock that bad.
The second paper had a curious section: > the jitter of the cycle out pulse generated by a link chip is around > 1ns when > the observed node is not a cycle master. > This statement is difficult to understand without concluding that what > is being > measured is not the sort of jitter that is being discussed in this > paper. I know how they feel..........! Pat -- ar-t http://www.analogresearch-technology.net ------------------------------------------------------------------------ ar-t's Profile: http://forums.slimdevices.com/member.php?userid=13619 View this thread: http://forums.slimdevices.com/showthread.php?t=56425
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