As you noticed, the interface between Beagle & FPGA is mostly
uncommitted. There are a few options that stand out:
* McSPI3 - this is a 1-bit serial stream, simultaneous I/O which
supports up to 48Mbps. SPI is inherently packetized and so may not be
ideal for isochronous streams like one often finds in SDR.
* McBSP3 - this is a 1-bit serial stream with simultaneous I/O that also
includes framing. It can operate up to 48Mbps in several different
modes, some of which support isochronous streams. This seems like it
would be ideal for SDR, especially since the McBSP can be piped into the
on-chip C6x DSP.
* MMC2 - this is an 8-bit parallel stream with muxed I/O and separate
commands that is primarily intended for communication with MMC/SD/SDIO
cards. With some creative FPGA wrapper logic and corresponding driver
code in the OMAP MCU it could conceivably be adapted to a fairly high
bandwidth packetized interface that could support fairly high data rates
- a quick skim of the TRM suggests a maximum clock frequency of 52MHz
for a theoretical data rate of 52MBps, but there's a fair amount of
handshaking involved with the SD protocols that would cut the aggregate
down from that considerably. Also, the current interface allocation
between Beagle and FPGA is not optimized to use this interface, so a
minor circuit revision would be required to explore this.
Eric
On 05/18/2010 11:49 AM, Stephen Hersey wrote:
Here's a question: What I/O do tyou plan to use between the FPGA and
BeagleBoard? From the schematic, it seems evident that you can use one
or more McBSPs (which ought to be good for SDR data traffic); do you
also envision doing parallel I/O?
On Tue, May 18, 2010 at 2:30 PM, Eric Brombaugh <[email protected]
<mailto:[email protected]>> wrote:
Hi,
A quick status on the Beagle FPGA project:
Boards are back from the PCB fab and the first one has been
assembled and is being tested. Configuration software is available
and the board is working with both the Angstrom Stable and Unstable
development trees. So far all power, ID, clocking and configuration
support circuitry is working as designed. Off-board I/O and the
remaining Beagle interface remains to be tested.
Find out more about this project at the following sites:
http://members.cox.net/ebrombaugh1/embedded/beagle/beagle_fpga.html
http://www.elinux.org/BeagleBoard_Tracker
Please let me know if you have any questions or comments on this.
Thanks,
Eric
--
Steve Hersey N1XNX
[email protected] <mailto:[email protected]>
-----
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