Hi, 
I never tried to read several ADC channels "simultaneously", but as far as 
I understand the TRM section on this, there is really only one hardware ADC 
witht multiplexer to make 8 channels. One acquisition takes at least 15 ADC 
clock cycles (625ns), that is for 6 channels, you would have to read one 
value after the other, giving you a 625 ns delay between subsequent values 
and a maximum 6-channel-samling rate of 1/3750ns = roughly 250kHz. As said 
above, jitter won't be too much of a problem here. Since the readout of the 
FIFO buffer also induces some delay, you should more realistically consider 
200-250 kHz. 
So if you can tolerate the delay of digitalization of the different analog 
inputs, the integrated ADC will work, otherwise you should consider using 
an external ADC. 


On Wednesday, July 23, 2014 9:07:52 PM UTC+2, sun19...@gmail.com wrote:
>
> Hello, Lenny,
> your solution is good, thanks. Here is another question : is it capable of 
> synchronizing "multiple" ADC channels at one time ?
>
> I have read ADC driver limitation from TI :
>
> http://processors.wiki.ti.com/index.php/AM335x_ADC_Driver%27s_Guide#ADC_Driver_Limitations
>
> and you said that I can use the ADC in single-acquisition mode. -> Is it 
> capable of synchronizing "multiple channels" at one time? (because I need 
> to sample three-phase current and voltage signal, so the sum of them are 6 
> channels.)
>
> I am not sure "single-acquisition" is limitation of hardware (ADC) 
> naturally or just limitation of driver function? 
> If I use single-acquisition mode, then I need to consider the effect of 
> conversion time between one channel and another channel.
>
>
> Finally, If I could, please send your sample code for me to my gmail.  
> Thanks!
>
>

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