Rob,
1) There is a FAB layer in the gerbers that shows the stackup used. The
stackup will vary with the board shop used - based on their processes and
the board material you specify and its dielectric constant.
2) This again can vary depending on the board shop - dielectric constant
and trace thickness contribute to width for controlled impedance traces.
For differential - gap is also important.
3) As stated, teardrops can be used for added strength, they can also be
used to limit breakout to the trace - so as tolerances in drilling vary,
the hole won't break the connection to the
trace - annular ring also comes into play with this - if you have
enough annular ring, you won't need to have teardrops to aid in breakout to
the trace - or in general.
4) Yes, I modified the design - there are plenty of places for traps and
gotchas. Depends on how much you are varying the design.
Be mindful of plane breaks and high speed signals when rerouting
traces. To reduce noise, make sure your signals have return/ground paths
that can follow closely to the trace.
Be mindful of length matching on your high speed interfaces. On your
prototypes, put current sense resistors inline with each power rail to aid
in debug of power issues - can remove later.
Try not to modify the DDR3 routing if possible - it works - only
modify what you need for process variation on the pcb build.
That's all I can think of for now.
Good Luck with your design.
Matt
On Tuesday, January 19, 2016 at 7:01:11 AM UTC-6, Rob wrote:
>
> Hi All,
>
> I'm currently modifying RevC / PCB Rev B6 for integration into a custom
> design. I have a few questions if others could provide input.
> The design is imported into Altium, and I feel there may be some missed
> PCB settings during the import.
>
> *1. Layer Stackup + Copper thickness* - Are there any details on the
> layer stackup + copper used? I would imagine this could impact some of he
> high speed / memory interfaces etc..
>
>
> *2. Minimum track width *- The following nets have 3.75mil tracks vs most
> other nets with 4.75mil thickness.
> HDMI_Tx(x) lines.
> DDR_DQS(n)(x) lines
> DDR_CLK lines
>
> Is there any issues using these thicknesses with standard 4/4 PCM
> Manufacturing processes. Or does this require specialised manufacturing.
> Would making these lines 4+mil have much effect on signal integrity ?
>
>
> *3. Wedge shaped pad connects* - On some tracks, the pad connections have
> a wedge shape meeting the track as shown below. I haven't seen this before,
> what is the reason for this ?
>
>
> <https://lh3.googleusercontent.com/-VCacqeV7XRw/Vp2zSPx38VI/AAAAAAAAIgA/9-4dP5Trf5s/s1600/via_wedge_connection.jpg>
>
>
> *4. Any other advice ?*
> Has anyone done this before ? Are there any traps or other gotchas I Need
> to be looking out for ?
>
> Thanks in advance for your help.
> Rob.
>
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