On Monday, 20 February 2017 01:51:53 UTC+1, ags wrote: > > Is it correct that whenever the PRU cores access any resource through the > 32-bit system but, it is subject to varying delay since the other PRU core > and even the ARM core (through the OCP slave, for instance if the ARM is > pushing data to the PRU 8k or 12k DRAM) may also be contending for control > of that bus? >
TI's "VBUS" interconnects aren't actual buses, they use crossbar switches, which means stalls should only happen if two initiators simultaneously try to access the same target. Probably there are priority rules then, similar to when two cores try to access the same scratchpad. This is something you could test fairly easily, e.g. let both cores repeatedly access one of the memories and compare their stall counts. Using multi-word vs single-word accesses might also have influence. There is also an undocumented priority config register for the pru interconnect you can try playing with, at offset 0x24 in pruss cfg module. Bits 0-7 are four 2-bit values presumably related to the four initiators (pru core 0, pru core 1, L3, and the unused pruss-to-pruss port), and bits 8-21 are 1-bit values presumably related to the targets. I don't know what the values actually mean :) Matthijs -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/4e4f777f-6b7f-4b2a-a819-00cf3ed027a9%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
