saksham balsane commented on a discussion on bsps/riscv/riscv/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145721 > > if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { > #ifdef RISCV_USE_S_MODE > - *pending = (read_csr(sip) & SIP_STIP) != 0; > + set_csr(sie, SIP_SSIP); > #else > - *pending = (read_csr(mip) & MIP_MTIP) != 0; > + set_csr(mie, MIP_MSIP); hi @opticron for pointing out the issue where the code for software interrupt path was checking SIP_STIP instead of SIP_SSIP. i will update the revised patch shortly which replaces the incorrect csr bit while preserving the orignal logic -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145721 You're receiving this email because of your account on gitlab.rtems.org.
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