saksham balsane commented on a discussion on bsps/riscv/riscv/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145727 > > if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { > #ifdef RISCV_USE_S_MODE > - *pending = (read_csr(sip) & SIP_STIP) != 0; > + set_csr(sie, SIP_SSIP); > #else > - *pending = (read_csr(mip) & MIP_MTIP) != 0; > + set_csr(mie, MIP_MSIP); the intent of change was only to correct the csr bit used when checking for a pending software interrupt the orig code was checking SIP_STIP which corresponds to the supervisor timer interrupt while this is meant to check the supervisor software interrupt .. the logic should therefore still read the the csr to determine whether the interrupt is pending. replacing the read with set_csr() was incorrect since that changes the interrupt state instead of querying it -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145727 You're receiving this email because of your account on gitlab.rtems.org.
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