Gedare Bloom commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1181#note_147916 I don't think it is practically possible to compile risc-v BSPs without defining the `RISCV_RAM_REGION_BEGIN` and `RISCV_RAM_REGION_SIZE` so it might be better to remove the FDT-based and linker script based code (currently in the `#else`) as it is probably dead code. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1181#note_147916 You're receiving this email because of your account on gitlab.rtems.org.
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