Kinsey Moore commented on a discussion on bsps/riscv/esp32/include/c6/chip_definitions.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148269 > +#include <bsp.h> > + > +#endif /* ASM */ > + > +/* > + * References: > https://documentation.espressif.com/esp32-c6_technical_reference_manual_en.pdf#intmtrx > + * The interrupt matrix supports 77 interrupts. The count of 78 below > includes 77 peripheral interrupts plus > + * invalid interrupt 1? > + * Chapter 10 - Interrupt Matrix - Page 379 > + */ > +#define RISCV_MAXIMUM_EXTERNAL_INTERRUPTS 78 > +#define BSP_INTERRUPT_VECTOR_COUNT RISCV_MAXIMUM_EXTERNAL_INTERRUPTS > + > +#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR > + > +// Table 10.3-1. CPU Peripheral Interrupt Source Mapping - page 380 Also address this elsewhere. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148269 You're receiving this email because of your account on gitlab.rtems.org.
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