Kinsey Moore started a new discussion on bsps/riscv/esp32/include/c6/chip_definitions.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148270 > + * SUCH DAMAGE. > + */ > + > +#ifndef LIBBSP_ESP32_C6_CHIP_DEFINITIONS_H > +#define LIBBSP_ESP32_C6_CHIP_DEFINITIONS_H > + > +#ifndef ASM > + > +#include <bsp.h> > + > +#endif /* ASM */ > + > +/* > + * References: > https://documentation.espressif.com/esp32-c6_technical_reference_manual_en.pdf#intmtrx > + * The interrupt matrix supports 77 interrupts. The count of 78 below > includes 77 peripheral interrupts plus > + * invalid interrupt 1? It looks like this may vary on the C6. On the C3, interrupt 0 is reserved for exceptions. The C6 supports CLINT which occupies CPU interrupts 0,3,4,7 of which only 3 and 7 are important for M-mode operation. The implementation here will be more complicated than the C3 because the RTEMS-facing interrupt management will need to take these into account whereas on the C3 there were *only* external interrupts and no CLINT. This will likely affect the publicly advertised interrupt values below. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148270 You're receiving this email because of your account on gitlab.rtems.org.
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