Kinsey Moore commented on a discussion on bsps/riscv/esp32/include/c6/chip_definitions.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148271 > + * SUCH DAMAGE. > + */ > + > +#ifndef LIBBSP_ESP32_C6_CHIP_DEFINITIONS_H > +#define LIBBSP_ESP32_C6_CHIP_DEFINITIONS_H > + > +#ifndef ASM > + > +#include <bsp.h> > + > +#endif /* ASM */ > + > +/* > + * References: > https://documentation.espressif.com/esp32-c6_technical_reference_manual_en.pdf#intmtrx > + * The interrupt matrix supports 77 interrupts. The count of 78 below > includes 77 peripheral interrupts plus > + * invalid interrupt 1? Instead of 77 peripherals + 1 for invalid interrupt 0, this is more likely to be 77+4 to be able to identify unique interrupt sources. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148271 You're receiving this email because of your account on gitlab.rtems.org.
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