Issue created by Sebastian Huber: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5742
The Malta board cannot run the test suite. Six defects stand in the way. The BSP links the software CPU counter of `bsps/shared/dev/cpucounter/`. `_CPU_Counter_read()` of that counter increments a static variable per call, so nothing in it measures time. The clock driver sets `CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER`, so the uptime advances once per clock tick and nothing resolves an interval below the tick. `Clock_driver_support_at_tick()` sets the compare register ahead of the count register, so every period gains the latency of the interrupt. Measured over 100 ticks, a period of 100000 counts takes 100277. `bsp_start()` sets the status register to `SR_FR | SR_PE`. `SR_FR` selects the 64 bit floating point registers, while the ELF attributes of every executable state a CPR1 size of 32. A double loses half of its bits on the way to memory and back. The same write clears `SR_CU1`, and `SR_PE` is a bit of the R3000 which the MIPS32 status register does not carry. `mips_interrupt_mask()` returns `0x0000ff00`, which enables line 7 of the processor. That line belongs to the compare register. Count and compare are both zero after a reset, so the line is asserted from the first instruction. An executable which needs no clock driver takes the interrupt, finds no handler and terminates with `RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT`. The BSP links the stubs of `bsps/mips/shared/irq/irqstubs.c`, so every interrupt controller directive fails. Its dispatcher prints a line for six of the eight sources of the processor rather than passing them to the interrupt manager. Its `tm27.h` is the default header, which raises no interrupt. The context switch of the MIPS port keeps the coprocessor enable of the floating point unit as a bit of the task. `setjmp()` of a hard float ABI saves the callee saved registers of the unit, so a task without `RTEMS_FLOATING_POINT` takes a coprocessor unusable exception inside `setjmp()`. Found while checking whether the Malta board can join a simulator test programme. This description was created with Claude Code assistance. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5742 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/sent_notifications/5-3aqcbtaf4w40que919gic7pfp-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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