> Hi
>
> Thanks of prompt response
> I have compared the schematics of both versions . The clock pins are kept
> the same.
> I compiled the bof files using the rev 2 ucf file.
Hi Homin.
We are successfully using the ASIAA 5 GS/s ADC and Rev 2 roach together
using the ADC clock input. Maybe Glenn Jones or Mark Wagner can comment
on the yellow blocks we're using.
John
>
> Homin
>
>
> Henno Kriel ©ó 2013¦~4¤ë18¤é¬P´Á¥|¼g¹D¡G
>
>> Hi Homin
>>
>> There was a change to the routing from the ZDOK pins to the FPGA from
>> rev1
>> to rev2.
>> Are you still running a design that was compiled for rev1?
>>
>> Regards
>> Henno
>>
>>
>> On Thu, Apr 18, 2013 at 2:22 PM, Homin Jiang
>> <ho...@asiaa.sinica.edu.tw<javascript:_e({}, 'cvml',
>> 'ho...@asiaa.sinica.edu.tw');>
>> > wrote:
>>
>>> Hello:
>>>
>>> After couple of tests, we found that the ADC clock signal is not able
>>> enter to the ROACH2 Rev 2. We physically measure the clock pin on ZDOK
>>> (F19,F20) of one 5G adc board which was plugged into Rev 1 and then Rev
>>> 2.
>>> In the Rev 1, there is clock signal, but no signal in the Rev 2.
>>>
>>> 4 of ROACH2 Rev. 2 have been tested by 10G ethernet bof file which used
>>> the system clock. The Rev 2 boards are working well in that case. The
>>> only
>>> difference i know is the Rev 1 is under tcpborphserver 2 , and the Rev
>>> 2 is
>>> under tcpborphserver 3. Is there IO bank control in the tcpborphserver
>>> 3 ?
>>>
>>> regards
>>> homin jiang
>>>
>>>
>>
>>
>> --
>> Henno Kriel
>>
>> DSP Engineer
>> Digital Back End
>> meerKAT
>>
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>>
>
