Hi Jonathan and all:
Thanks of inform me the bug that is the exact fault caused the malfunction.
We just had a good luck while running Rev 1, turned out we didn't pay
attention to it.
So, please check the R104 and R105 if you are using the 5G adc.
cheers
homin
On Fri, Apr 19, 2013 at 11:02 AM, Jonathan Weintroub <
jweintr...@cfa.harvard.edu> wrote:
> Hi Homin,
>
> One other thing to check is the resistor locations R104 and R105.
>
> -->R104 should be unpopulated.
>
> -->R105 should be populated with 0 ohm.
>
> When checking this note that the silkscreen markings are quite ambiguous.
> So identify R104 explicitly by noting that one side of it goes to pin 7 of
> U2 etc.
>
> In an early build of the ADCs we had similar trouble due to these two
> sites being mixed up by the assembler.
>
> If R105 is indeed missing, the needed reset does not get to the input of
> buffer U3 even if you are using the correct bitcode which provides that
> reset.
>
> Jonathan
>
>
>
> On Apr 18, 2013, at 10:27 PM, Homin Jiang wrote:
>
> > Dear Rurik:
> >
> > I downloaded the library from github/ska-sa at Jan 21,2013.
> > Could you specify where is the floating reset line ? that might give me
> some hints.
> >
> > Dear Mark and Glenn:
> >
> > Could you share me what you have done ? That might save me couple of
> days.
> >
> > cheers
> > homin
> >
> >
> >
> > On Thu, Apr 18, 2013 at 11:09 PM, Rurik A Primiani <
> rprim...@cfa.harvard.edu> wrote:
> > Hi Homin,
> >
> > What version of the yellow block are you using?
> >
> > We had an issue with the clock not coming through due to a floating
> reset line that was not being driven. This was fixed a while ago on
> sma-wideband/mlib_devel and I believe has also been merged into the main
> casper-astro repository.
> >
> > Thanks,
> > Rurik
> >
> >
> > On 4/18/2013 10:49 AM, John Ford wrote:
> > Hi
> >
> > Thanks of prompt response
> > I have compared the schematics of both versions . The clock pins are kept
> > the same.
> > I compiled the bof files using the rev 2 ucf file.
> > Hi Homin.
> >
> > We are successfully using the ASIAA 5 GS/s ADC and Rev 2 roach together
> > using the ADC clock input. Maybe Glenn Jones or Mark Wagner can comment
> > on the yellow blocks we're using.
> >
> > John
> >
> > Homin
> >
> >
> > Henno Kriel 於 2013年4月18日星期四寫道：
> >
> > Hi Homin
> >
> > There was a change to the routing from the ZDOK pins to the FPGA from
> > rev1
> > to rev2.
> > Are you still running a design that was compiled for rev1?
> >
> > Regards
> > Henno
> >
> >
> > On Thu, Apr 18, 2013 at 2:22 PM, Homin Jiang
> > <ho...@asiaa.sinica.edu.tw<javascript:_e({}, 'cvml',
> > 'ho...@asiaa.sinica.edu.tw');>
> > wrote:
> > Hello:
> >
> > After couple of tests, we found that the ADC clock signal is not able
> > enter to the ROACH2 Rev 2. We physically measure the clock pin on ZDOK
> > (F19,F20) of one 5G adc board which was plugged into Rev 1 and then Rev
> > 2.
> > In the Rev 1, there is clock signal, but no signal in the Rev 2.
> >
> > 4 of ROACH2 Rev. 2 have been tested by 10G ethernet bof file which used
> > the system clock. The Rev 2 boards are working well in that case. The
> > only
> > difference i know is the Rev 1 is under tcpborphserver 2 , and the Rev
> > 2 is
> > under tcpborphserver 3. Is there IO bank control in the tcpborphserver
> > 3 ?
> >
> > regards
> > homin jiang
> >
> >
> >
> > --
> > Henno Kriel
> >
> > DSP Engineer
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> >
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>
