Hi,
I have trouble to compile the adc clock rate of asiaa_adc5g block at
2500MHz.
Block parameter: two-channel, ZDOK0, demux 1:1 .
System: roach2, clock source:adc0_clk, clock rate: 312.5MHz)
The error is as follows:
Creating block object: xps_adc5g
Problem with block: lab_test_adv5/asiaa_adc5g1
: An optimum PLL solution is not available!
Backtrace 1: xps_adc5g:175
Backtrace 2: gen_xps_files:229
Backtrace 3: run_Callback:149
Backtrace 4: casper_xps:82
Backtrace 5:
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject)):0
Error using gen_xps_files (line 242)
Error found during Object creation.
There are a bunch of frequency justification in the xps_adc5g.m that I just
can't understand. Could some one give me some suggestions on the error or
the codes? Does it mean that the 5G adc can't run at 2.5GHz?
Any help or suggestions are very appreciated!
Weiwei
