I'm not sure what, if any, difference a subsystem will make to the mapped design (I thought none), but I believe it's the case that changing module names etc. can affect the place and route algorithm's start seed. I seem to remember seeing this mentioned in a Xilinx doc under the heading "I've saved my project under a different name, now it won't meet timing, wtf?!"
On 29 January 2014 22:44, John Ford <jf...@nrao.edu> wrote: >> >> On 01/29/2014 01:03 PM, Paul Marganian wrote: >>> Hi all, >>> Should such software (simulink) features as subsystems and and gotos >>> have any affect on the final circuit created when I build my bof file? >>> >>> I am compiling models on Roach I that use almost all of the available >>> Logic Slices (~97%). That the subsequent build should contain timing >>> errors is not a surprise, but I recently noted a change in my timing >>> errors that puzzled me. >>> >>> I have assumed up till now that certain types of features in my model >>> are superficial, and will not change how the bof file is built. I >>> wanted to test this theory, and rebuilt my model after selecting part >>> of my model and turning it into a subsystem. I was surprised to see >>> that this new build had very different timing errors then the previous >>> one (from 18 errors to just 3). >>> >>> Is it the subsystem that caused this change, or is another one of my >>> assumptions, that timing errors are deterministic and can be >>> reproduced with subsequent builds of identical models, false? >> I've made a test of this, and indeed, I think my assumption is correct: >> I get the same timing errors after two subsequent builds. > > Try saving the model and compiling it again, just changing a comment or > something else non-substantive. > > John > >> >>> >>> thanks >>> Paul Marganian >>> NRAO, Green Bank >>> >>> >> >> > > >
