Hi Marc, Can you expand on this a bit. Are you saying that I should set the top bits of the DRAM address in the FPGA fabric and that will then affect the 256 MB portion of the DRAM that is accessed by the PPC, which is then broken up into the 64 MB chunks described in the block documentation and accessed with the dram_controller register? That seems counter-intuitive.
Jason, I looked at the read_dram and write_dram functions, and that's basically the way my code works. I was hoping to see some secret extra register setting I was missing to explain the behavior I'm seeing. Thanks again for the input on this problem. Hopefully I'll figure it out eventually. Glenn On Tue, Feb 25, 2014 at 2:43 AM, G Jones <glenn.calt...@gmail.com> wrote: > Hi Marc, > Thanks for the reply. I would have expected that selecting the 64 MB chunk > with the dram_controller register as described in the DRAM block > documentation on the wiki would get around any such PPC address space > limitation. Is that not the case? > > Glenn > On Feb 25, 2014 2:30 AM, "Marc Welz" <m...@ska.ac.za> wrote: > >> On Mon, Feb 24, 2014 at 7:57 PM, G Jones <glenn.calt...@gmail.com> wrote: >> > Hi, >> > Sorry to repost this. Just curious if anyone has experience using more >> than >> > 256 MB of FPGA DRAM on the ROACH, in particular through the PPC >> interface. >> >> The PowerPC's virtual memory subsystem maps things in 256Mb >> regions/segments, >> and only one is used to access the FPGA(*) - so you will probably have >> to implement >> some sort of windowing/base+offset scheme. >> >> (The address space of the PowerPC is pretty constrained) >> >> regards >> >> marc >> >
