Hi all, I'm trying to use QDR on Roach2. I have a test design where I write to QDR either in firmware or with katcp, then read it out in the firmware and check the results with snapshot blocks. It mostly works, but with some interesting quirks.
I know that katcp can only write 64 bits of the 72 bit QDR word, so I changed the bitbasher blocks in qdr_mask.m to move the inaccessible bits out of the way to the most significant bits. Now everything seems to work well, except that in some builds (seems to depend on clock rate?), the first 32 bits (of the 64 bits I'm writing in a cycle) get swapped with the last 32 bits sometime between writing the word and reading it back. And there is a sometimes a difference in whether I am writing in firmware or by katcp to whether this swap happens. Also, when I write with katcp starting at address zero, I find that when reading out, the write started at what seems to be address 1. Is the latency of QDR set to 10 cycles? I can live with all this, as long as it is repeatable for a given design, but I thought I'd ask if anyone knows what is causing these quirks. Also, I understand that we should run a software calibration for qdr, which seems to be qdr_cal() in qdr.py in the ska-sa:casperfpga repo. So, I run this first, which seems to work for my latest compiles, but I haven't noticed a difference in the results. What exactly does this calibration do? Thanks, Matt Strader UC Santa Barbara
