hi andrea, developing everything exclusively in VHDL for a casper board is hard, as jack pointed out.
but there's a way that is fairly easy, perhaps you already know, where you could develop most of your code in VHDL or Verilog, but you'd still need a bit of simulink to wrap your code: it's fairly easy to put your VHDL code into a simulink "block box" block - you can make as many block boxes as you want, and then interconnect these blocks in simulink with the casper yellow input/output blocks and compile your design using the casper tool flow. see: Tutorial 6: Introduction to embedding Verilog within a Simulink design.This tutorial gives a brief introduction to embedding Verilog (or VHDL) code in your Simulink models using the Xilinx "Black Box" block. best wishes, dan <https://github.com/casper-astro/tutorials_devel/tree/master/tut6> <https://github.com/casper-astro/tutorials_devel/tree/master/tut6> <https://github.com/casper-astro/tutorials_devel/tree/master/tut6> <https://github.com/casper-astro/tutorials_devel/tree/master/tut6> On Wed, Jun 22, 2016 at 12:47 AM, Jack Hickish <jackhick...@gmail.com> wrote: > Hi Andrea, cc-ing maillist, since I don't think you're the only one to do > (or want to do) this, > > What you are suggesting is absolutely technically possible, though (as > much as I dislike simulink), I'd think really hard before going through > with it. Note also, if you don't use the toolflow, you become completely > responsible for managing the FPGA's memory-mapped devices, and will have to > manually build a boffile if you want to use the katcp/borphserver > programming environment. That said, others may already have done all the > legwork for you. > > Anyway, with that cautionary note.... > > The VHDL (or verilog) for the various CASPER blocks is available as part > of the various pcores of the roach2 base package -- > https://github.com/casper-astro/mlib_devel/tree/master/xps_base/XPS_ROACH2_base/pcores > . > > The instantiation of these interface blocks is performed by the toolflow > at compile time, which generates a Xilinx EDK spec system.mhs top level > file. If you want to find out how to instantiate these blocks yourself, > using the toolflow as a guide, here is where you climb into the CASPER > rabbit hole. > > There is an EDK template for a compile in the base package: for ROACH2 -- > https://github.com/casper-astro/mlib_devel/blob/master/xps_base/XPS_ROACH2_base/system.mhs > . > In theory, if you strip out the #IF#s in this file, you'll have a top-level > model description you can add stuff to -- but it still won't be in VHDL, > even if the instantiated modules are. Constraints are in > https://github.com/casper-astro/mlib_devel/blob/master/xps_base/XPS_ROACH2_base/data/system.ucf > > The toolflow adds to this template in a variety of ways -- > * individual yellow blocks can add code via the MATLAB object-oriented > infrastructure via the gen_mhs_ip and gen_ucf methods of the xps class -- > eg. > https://github.com/casper-astro/mlib_devel/tree/master/xps_library/%40xps_adc5g > * or via an overridden gen_mhs_ip or gen_ucf -- eg. > https://github.com/casper-astro/mlib_devel/blob/master/xps_library/%40xps_bram/gen_mhs_ip.m > * or via all the #IF# statements in the base package system.mhs/system.ucf > > If (#IF#?) you want to dig through the matlab block classes, and > system.mhs looking for what a particular yellow block *does* when it is > instantiated, you probably could. But it will still be an EDK file, not > vhdl. > You could also fire up simulink, compile a design with appropriate yellow > blocks in and then grab the system.mhs it generates and use that as a > template. > You could also look in an old ROACH2 testing repository where firmware was > tested prior to being casperized -- > https://github.com/ska-sa/roach2_test_gateware/blob/master/modules/toplevel/hdl/toplevel.v > which > is all VHDL/Verilog, but probably doesn't have all the modules you need. > > You might find the yellow block casper tutorial is useful in figuring out > where various aspects of the interface code is instantiated. > > As a final note -- the latest version of the Vivado-based CASPER toolflow > (aka, JASPER), includes (thanks, Adam & Wes in SA!) the ability to generate > an ISE-spec project (i.e., a ucf file and a top level verilog file) from a > simulink model. I don't know which yellow blocks are currently supported > for ROACH2, but if the ones you need work, this is probably the easiest > route to generating a template ISE project. If this is the way you want to > go, we should talk more somewhere. But you should be aware that you'll be > placing yourself on the bleeding edge, where things are, well, bloody. > > Cheers, > > Jack > > On Tue, 21 Jun 2016 at 06:06 Andrea Melis <andrme...@gmail.com> wrote: > >> Hi Jack, >> >> how are you doing? >> >> I would ask you a question, I am interested in developing projects fully >> in VHDL into the ROACH2 (equipped with ADC 5GS and mezzanine cards SFP+), >> is available the VHDL code for the various blocks of the CASPER library? Is >> the code generated after the compiling? >> >> In particular I would need a “template” VHDL containing especially the >> I/O parts like the ADCs and the 10 Gbe outputs blocks, in order to have a >> VHDL skeleton as a starting point for whatever digital signal processing >> on-chip. >> >> Please let me know whether it already exists or whether it can be >> technically done, I thank you in advance >> >> Cheers >> >> >> Andrea >> >
