Hi dan, Thank you for your immediate response. In the fft_biplex_real blocks also they have at least two simultaneous input paths. So how can I split the one channel ADC output stream(200MHz) into multiple paths to give it to FFT block? Even if i find a method to do that, It will reduce the sampling rate of the input stream no?
I am using ROACH2 revision 2 board. It has two 16 channel ADC cards. I want to calibrate both the ADC cards at the same time. That’s why I mentioned as 32 channel ADC calibration. Thank you. Sivasankar.S On Mon, Mar 18, 2024 at 11:10 PM 'Dan Werthimer' via casper@lists.berkeley.edu <casper@lists.berkeley.edu> wrote: > > hi sivakumar, > > for low sample rate FFT's (where the FPGA clock = sample rate), i suggest > you consider: > fft_biplex_real_2x > <https://casper-toolflow.readthedocs.io/en/stable/src/blockdocs/Fft_biplex_real_2x.html> > (Real-sampled > Biplex FFT, with Output Demuxed by 2) > fft_biplex_real_4x > <https://casper-toolflow.readthedocs.io/en/stable/src/blockdocs/Fft_biplex_real_4x.html> > (Real-sampled > Biplex FFT, with Output Demuxed by 4) > > the various casper FFT's are listed here: > https://casper-toolflow.readthedocs.io/en/stable/blockdocumentation.html > > what is the 32 input ADC board you are trying to calibrate ? > is this the board designed by larry dedarrio for the LWA ? > > best wishes, > > dan > > > On Mon, Mar 18, 2024 at 7:53 PM Sivasankar <sivasiva8...@gmail.com> wrote: > >> Dear Caspers, >> Currently I am facing an issue with 32 ADC channel calibration >> with ROACH2 rev2 board. The script for 16-ADC channel calibration is >> working fine and it has calibrated successfully. I have used the same >> script and changed the 16 ADC design to 32 ADC channel. I have selected >> adc0_clk as the User IP clock and given 230MHz. But It is giving the below >> error. Can anyone please help me to debug this issue? >> >> Also, I want to design a FFT operation to a single channel from 16 ADC >> channels with a sampling rate of 200MHz. But I couldn't find any single >> input path FFT cores in casper library. All the FFT cores are coming with >> at least 4 simultaneous input paths with a single simultaneous input >> stream. Are there any possible blocks with a single input path so that I >> can do FFT(clocking with fabric clk 200MHz) to a 200MHz single channel from >> the ADC output? >> >> Thank you in advance >> >> Sivasankar.S >> >> -- >> You received this message because you are subscribed to the Google Groups >> "casper@lists.berkeley.edu" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to casper+unsubscr...@lists.berkeley.edu. >> To view this discussion on the web visit >> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAOQNGP03dv_SsJF6Cpva7na35iLhAV_YMkETOBGVAVgQTce-Mg%40mail.gmail.com >> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAOQNGP03dv_SsJF6Cpva7na35iLhAV_YMkETOBGVAVgQTce-Mg%40mail.gmail.com?utm_medium=email&utm_source=footer> >> . >> > -- > You received this message because you are subscribed to the Google Groups " > casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAA9jdzJWg6KLMavAM-C%3Dijmv%3DqkrkMUqA5Cqo0qYqYacn35uog%40mail.gmail.com > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAA9jdzJWg6KLMavAM-C%3Dijmv%3DqkrkMUqA5Cqo0qYqYacn35uog%40mail.gmail.com?utm_medium=email&utm_source=footer> > . > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAOQNGP1X%3DA3L77E0_Drpxjd3TO1hbj2eh440iZJiV2Yf60QSNQ%40mail.gmail.com.