Hi Vereese,

I didn’t expect that link to point to the UArizona work on interleaving, but it 
does, and your question gets at what we had to work out, so I will comment a 
little. For Arash’s thesis work (he’s Dr. Roshanineshat now), we did interleave 
pairs of ADCs on the ZCU111. This required enabling the external clocking and 
building a board to send separate clocks to the four tiles. There is no way to 
interleave a pair of ADCs on the same tile, but by shifting the clock phase 
between two tiles you can interleave ADCs in pairs between tiles. Arash can 
make his thesis available 
aroshanines...@arizona.edu<mailto:aroshanines...@arizona.edu> and David Forbes 
designed the board dfor...@arizona.edu<mailto:dfor...@arizona.edu> and both are 
on this list. Someday very soon we will feel that our interleaving board design 
is tested enough and find a way to make the design available through CASPER.

Dan

On Jan 9, 2025, at 05:55, Vereese Van Tonder 
<vere...@sarao.ac.za<mailto:vere...@sarao.ac.za>> wrote:


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Great, thanks Jack. So one can safely interleave 2 ADCs (both located within 1 
tile) upto 8 GSPS for 4 separate inputs.

Have a good one.


On Thu, Jan 9, 2025 at 2:49 PM Jack Hickish 
<jackhick...@gmail.com<mailto:jackhick...@gmail.com>> wrote:

(Though see 
https://adaptivesupport.amd.com/s/question/0D52E00006hpOwBSAU/rfsoc-multitile-adc-interleaving?language=en_US<https://adaptivesupport.amd.com/s/question/0D52E00006hpOwBSAU/rfsoc-multitile-adc-interleaving?language=en_US>
 if interleaving is your desire)


On Thu, 9 Jan 2025, 12:43 Jack Hickish, 
<jackhick...@gmail.com<mailto:jackhick...@gmail.com>> wrote:

Hi Vereese,

Happy 2025!

The quoted 4G is per ADC, not per tile, so the ZCU111 really does have 8x4GSPS 
samplers. The total sampling rate is indeed 32 GSPS (but this doesn't mean that 
you can trivially interleave all 8 channels to achieve a single super-high 
sample rate)

Cheers
Jack

On Thu, 9 Jan 2025, 12:22 Vereese Van Tonder, 
<vere...@sarao.ac.za<mailto:vere...@sarao.ac.za>> wrote:
Hi ZCU111 users,

I'm looking at:
https://docs.amd.com/r/en-US/ug1271-zcu111-eval-bd/SI5382A-SFP28-Clock-Recovery<https://docs.amd.com/r/en-US/ug1271-zcu111-eval-bd/SI5382A-SFP28-Clock-Recovery>
which states:
"The ZU28DRF-FFVG1517 contains eight multi-gigasample (4 GSPS), 12-bit RF 
analog-to-digital converter (RF-ADC) channels across four banks"

>From this I understand that a ZCU111 board can provide upto 32 GSPS - is this 
>correct? Or does a tile (which contains 2 ADCs) provide 4GSPS in total, i.e. 
>each is clocking at only 2GSPS and therefore the board can provide 16 GSPS in 
>total?

Thanks in advance and happy 2025.



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