Hi Matthew,
There is a fourth way to correct the interleaving problems. This is to
send the input signal also to an additional ADC that is running at a
sampling rate that isn't a multiple of any of the others.
For example, one might want to interleave two 5GHz ADCs to get an
effective 10GHz sampling rate. To do this, have one ADC sampling at
5GHz, a second ADC also at 5GHz (with either the sampling times offset
or with an analog delay on the input signal), and a third ADC sampling
at 4GHz. All three ADCs sampling the same signal.
Having this extra 4GHz-sampled signal allows the linear effects that you
describe to be characterized on the other two 5GHz-sampled signals --
regardless of input. (Zero signal amplitude in a frequency range
obviously doesn't allow it, but in that case calibration is unnecessary
for that frequency range since the output for that frequency range is
zero.) Once characterized, the linear effects can be compensated and
the 5GHz-sampled signals can be corrected for proper interleaving.
I wouldn't say this approach is drawback-free. It requires more
processing -- possibly significantly more. It requires an extra ADC.
Matching the signals at different sampling rates is tricky. When
time-corrections are large, signal quality is reduced.
Regards,
Ross
On 1/9/25 07:29, Matthew Schiller wrote:
Just be careful with this approach…
Fundamentally interleaving ADCs, is similar to problems you have with
quadrature mixers and I/Q separation.
When you use two (or N) ADCs to sample at a higher rate, you introduce
multiple analog to digital paths, each of which behaves differently.
Gain: the amplitude of samples on one adc may not equal the amplitude
on the other ADC(s)
Phase: A delay or even worse Frequency dependent delay may be
introduced between ADC channels
Sample-hold leakage/Charge time: Related to Analog bandwidth, the ADCs
may not be able to sample the amplitude at the exact moment of the
clock edge, and tend to smear or average the power over a longer period.
When you interleave ADCs, you deliberately phase shift the sampling
clocks to make the ADCs behave as if they are at a higher sample rate,
but these problems come into play both on the clock path (where the
deliberate delay may not be what you expected) and on the analog path
through the digitizer.
If your goal is to literally digitize at 32GSPS, these effects can
cause you major problems as the coherency of samples between ADCs is
likely to be much less than you’d like, which causes artifacts (eg
replicas of the spectrum etc). Further you may need to verify the
analog bandwidth of the ADC, it may have significant gain-slope (Eg
reduction of amplitude at high frequency) which will also limit your
performance.
These artifacts CAN in theory be corrected by characterizing your RF
chain. There are algorithms (mostly behind proprietary company IP
built into commercial ADCs or in commercial Radio Receivers, but some
in the public domain or at least documented in public papers), to
correct these problems, but the algorithms fall into three broad
categories:
1. Versions that rely on the target signal characteristics. The
digital comm world have pretty much solved these problems, but the
adaptive algorithms they often use rely on a strong well known
signal, such as a cell phone carrier signal to correct the problems
2. Versions that rely on Guassian noise. If a receiver noise floor
is known Guassian (white), there are exists algorithms to exploit
that.
1. These are probably the most generic, but usually result in
SOME residual artifacts
3. Apriory Calibration (eg lab equipment signal sources)
1. Difficult, unless you can build test equipment into your hardware
2. Calibration is likely to change with temperature, from unit to
unit, and potentially over time.
Each of which has significant drawbacks depending on your application.
AB72FAB9
Matthew Schiller
ngVLA Digital Backend Lead
NRAO
mschi...@nrao.edu <mailto:mschi...@nrao.edu>
315-316-2032
*From:* casper@lists.berkeley.edu <casper@lists.berkeley.edu> *On
Behalf Of *Marrone, Dan - (dmarrone)
*Sent:* Thursday, January 9, 2025 8:49 AM
*To:* casper@lists.berkeley.edu
*Subject:* Re: [EXT] [casper] ZCU111 ADCs {External}
Hi Vereese,
I didn’t expect that link to point to the UArizona work on
interleaving, but it does, and your question gets at what we had to
work out, so I will comment a little. For Arash’s thesis work (he’s
Dr. Roshanineshat now), we did interleave pairs of ADCs on the ZCU111.
This required enabling the external clocking and building a board to
send separate clocks to the four tiles. There is no way to interleave
a pair of ADCs on the same tile, but by shifting the clock phase
between two tiles you can interleave ADCs in pairs between tiles.
Arash can make his thesis available aroshanines...@arizona.edu and
David Forbes designed the board dfor...@arizona.edu and both are on
this list. Someday very soon we will feel that our interleaving board
design is tested enough and find a way to make the design available
through CASPER.
Dan
On Jan 9, 2025, at 05:55, Vereese Van Tonder <vere...@sarao.ac.za>
wrote:
*External Email***
------------------------------------------------------------------------
Great, thanks Jack. So one can safely interleave 2 ADCs (both
located within 1 tile) upto 8 GSPS for 4 separate inputs.
Have a good one.
On Thu, Jan 9, 2025 at 2:49 PM Jack Hickish
<jackhick...@gmail.com> wrote:
(Though see
https://adaptivesupport.amd.com/s/question/0D52E00006hpOwBSAU/rfsoc-multitile-adc-interleaving?language=en_USif
interleaving is your desire)
On Thu, 9 Jan 2025, 12:43 Jack Hickish,
<jackhick...@gmail.com> wrote:
Hi Vereese,
Happy 2025!
The quoted 4G is per ADC, not per tile, so the ZCU111
really does have 8x4GSPS samplers. The total sampling rate
is indeed 32 GSPS (but this doesn't mean that you can
trivially interleave all 8 channels to achieve a single
super-high sample rate)
Cheers
Jack
On Thu, 9 Jan 2025, 12:22 Vereese Van Tonder,
<vere...@sarao.ac.za> wrote:
Hi ZCU111 users,
I'm looking at:
https://docs.amd.com/r/en-US/ug1271-zcu111-eval-bd/SI5382A-SFP28-Clock-Recovery
which states:
"The ZU28DRF-FFVG1517 contains eight multi-gigasample
(4 GSPS), 12-bit RF analog-to-digital converter
(RF-ADC) channels across four banks"
From this I understand that a ZCU111 board can provide
upto 32 GSPS - is this correct? Or does a tile (which
contains 2 ADCs) provide 4GSPS in total, i.e. each is
clocking at only 2GSPS and therefore the board can
provide 16 GSPS in total?
Thanks in advance and happy 2025.
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